EDSTRG28PLCCCX datasheet(69/78 Pages) TI

69 / 78 page

MECHANICAL DATA

4–3

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

mechanical data

Table 1 is designed to aid the user when referencing a device family to the mechanical data section. The table

shows a cross-reference of the device family to the TMS370 generic package names and the associated

mechanical drawing(s) by drawing number and name.

Table 1. TMS370 Family Package Type and Mechanical Cross-Reference

PACAKGE TYPE

(mil pin spacing)

TMS370 GENERIC NAME

PACAKGE TYPE NUMBER AND

MECHANICAL NAME

FAMILY MEMBERS†

FN – 28 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

TMS370Cx0x,

TMS370Cx1x, and

TMS370CxCx

FN – 44 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

TMS370Cx2x,

TMS370Cx32,

TMS370Cx36,

TMS370Cx4x,

TMS370Cx8x, and

TMS370Cx9x

FN – 68 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

TMS370Cx5x,

TMS370Cx6x,

TMS370Cx7x, and

TMS370CxBx

FZ – 28 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370Cx0x, SE370Cx1x,

and SE370CxCx

FZ – 44 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370Cx2x, SE370Cx32,

SE370Cx36, SE370Cx4x,

SE370Cx8x, and

SE370Cx9x

FZ – 68 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370Cx5x, SE370Cx6x,

and SE370Cx7x

JD – 28 pin

(100-mil pin spacing)

CERAMIC DUAL-IN-LINE PACKAGE

(CDIP)

JD(R-CDIP-T**) CERAMIC SIDE-BRAZE

DUAL-IN-LINE PACKAGE

SE370Cx1x and

SE370CxCx

JD – 40 pin

(100-mil pin spacing)

CERAMIC DUAL-IN-LINE PACKAGE

(CDIP)

JD(R-CDIP-T**) CERAMIC SIDE-BRAZE

DUAL-IN-LINE PACKAGE

SE370Cx2x and

SE370Cx4x

N – 28 pin

(100-mil pin spacing)

PLASTIC DUAL-IN-LINE PACKAGE

(PDIP)

N(R-PDIP-T**) PLASTIC DUAL-IN-LINE

PACKAGE

TMS370Cx1x and

TMS370CxCx

N – 40 pin

(100-mil pin spacing)

PLASTIC DUAL-IN-LINE PACKAGE

(PDIP)

N(R-PDIP-T**) PLASTIC DUAL-IN-LINE

PACKAGE

TMS370Cx2x,

TMS370Cx4x,

TMS370Cx8x, and

TMS370CxAx

JC – 40 pin

(70-mil pin spacing)

CERAMIC SHRINK DUAL-IN-LINE

PACKAGE (CSDIP)

JC(R-CDIP-T40) CERAMIC SIDE-BRAZE

DUAL-IN-LINE PACKAGE

SE370Cx2x, SE370Cx4x,

and SE370Cx9x

NJ – 40 pin

(70-mil pin spacing)‡

PLASTIC SHRINK DUAL-IN-LINE

PACKAGE (PSDIP)

NJ(R-PDIP-T**) PLASTIC SHRINK

DUAL-IN-LINE PACKAGE

TMS370Cx2x,

TMS370Cx4x, and

TMS370Cx9x

JN – 64 pin

(70-mil pin spacing)

CERAMIC SHRINK DUAL-IN-LINE

PACKAGE (CSDIP)

JN(R-CDIP-T64) CERAMIC

DUAL-IN-LINE PACKAGE

SE370Cx5x and

SE370Cx7x

NM – 64 pin

(70-mil pin spacing)

PLASTIC SHRINK DUAL-IN-LINE

PACKAGE (PSDIP)

NM(R-PDIP-T64) PLASTIC SHRINK

DUAL-IN-LINE PACKAGE

TMS370Cx5x,

TMS370Cx7x, and

TMS370CxBx

† TMS370Cxxx refers to ROM and OTP devices; SE370Cxxx refers to UV-EPROM devices

‡ NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.

EDSTRG28PLCCCX Datasheet(PDF) 69 Page - Texas Instruments

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