68HC05JB4 datasheet(29/134 Pages) FREESCALE

29 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

CENTRAL PROCESSING UNIT

MOTOROLA

REV 2

3-3

Normally, the address in the program counter increments to the next sequential

memory location every time an instruction or operand is fetched. Jump, branch,

and interrupt operations load the program counter with an address other than that

of the next sequential location.

3.6

CONDITION CODE REGISTER (CCR)

The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to

indicate the results of the instruction just executed. The ﬁfth bit is the interrupt

mask. These bits can be individually tested by a program, and speciﬁc actions can

be taken as a result of their states. The condition code register should be thought

of as having three additional upper bits that are always ones. Only the interrupt

mask is affected by a reset of the device. The following paragraphs explain the

functions of the lower ﬁve bits of the condition code register.

3.6.1 Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4

of the accumulator during the last ADD or ADC (add with carry) operation. The

half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.

3.6.2 Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled.

Interrupts are enabled when the interrupt mask is cleared. When an interrupt

occurs, the interrupt mask is automatically set after the CPU registers are saved

on the stack, but before the interrupt vector is fetched. If an interrupt request

occurs while the interrupt mask is set, the interrupt request is latched. Normally,

the interrupt is processed as soon as the interrupt mask is cleared.

A return from interrupt (RTI) instruction pulls the CPU registers from the stack,

restoring the interrupt mask to its state before the interrupt was encountered. After

any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit

(CLI), or WAIT instructions.

3.6.3 Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical

operation, or data manipulation was negative. (Bit 7 of the result was a logical

one.)

The negative bit can also be used to check an often tested ﬂag by assigning the

ﬂag to bit 7 of a register or memory location. Loading the accumulator with the

contents of that register or location then sets or clears the negative bit according

to the state of the ﬂag.

3.6.4 Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical

operation, data manipulation, or data load operation was zero.

Freescale Semiconductor, Inc.

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