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ADE9153AACPZ Datasheet(PDF) 34 Page - Analog Devices |
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ADE9153AACPZ Datasheet(HTML) 34 Page - Analog Devices |
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34 / 50 page  ADE9153A Data Sheet Rev. 0 | Page 34 of 50 Address Name Description Length (Bits) Reset Access 0x40F VLEVEL Register used in the algorithm that computes the fundamental reactive power. 32 0x0045D450 R/W 0x410 DIP_LVL Voltage RMS_OC dip detection threshold level. 32 0x00000000 R/W 0x411 DIPA Phase A voltage RMS_OC value during a dip condition. 32 0x007FFFFF R 0x414 SWELL_LVL Voltage RMS_OC swell detection threshold level. 32 0x00FFFFFF R/W 0x415 SWELLA Phase A voltage RMS_OC value during a swell condition. 32 0x00000000 R 0x418 APERIOD Line period on the Phase A voltage. 32 0x00500000 R 0x41C ACT_NL_LVL No load threshold in the total active power datapath. 32 0x00008225 R/W 0x41D REACT_NL_LVL No load threshold in the fundamental reactive power datapath. 32 0x00008225 R/W 0x41E APP_NL_LVL No load threshold in the total apparent power datapath. 32 0x00008225 R/W 0x41F PHNOLOAD Phase no load register. 32 0x00000000 R 0x420 WTHR Sets the maximum output rate from the digital to frequency converter of the total active power for the CF calibration pulse output. It is recommended to leave this at WTHR = 0x00100000. 32 0x00100000 R/W 0x421 VARTHR See WTHR. It is recommended to leave this at VARTHR = 0x00100000. 32 0x00100000 R/W 0x422 VATHR See WTHR. It is recommended to leave this value at VATHR = 0x00100000. 32 0x00100000 R/W 0x423 LAST_DATA_32 This register holds the data read or written during the last 32-bit transaction on the SPI port. 32 0x00000000 R 0x424 CT_PHASE_MEAS Set to 0xE5 for CT_PHASE_DELAY measurement; otherwise, the value must be 0xE4. 32 0x000000E4 R/W 0x425 CF_LCFG CF calibration pulse width configuration register. 32 0x00000000 R/W 0x471 TEMP_TRIM Temperature sensor gain and offset, calculated during the manufacturing process. 32 0x00000000 R 0x472 CHIP_ID_HI Chip identification, 32 MSBs. 32 0x00000000 R 0x473 CHIP_ID_LO Chip identification, 32 LSBs. 32 0x00000000 R 0x480 Run Write this register to 1 to start the measurements. 16 0x0000 R/W 0x481 CONFIG1 Configuration Register 1. 16 0x0300 R/W 0x485 ANGL_AV_AI Time between positive to negative zero crossings on Phase A voltage and current. 16 0x0000 R 0x488 ANGL_AI_BI Time between positive to negative zero crossings on Phase A and Phase B currents. 16 0x0000 R 0x48B DIP_CYC Voltage RMS_OC dip detection cycle configuration. 16 0xFFFF R/W 0x48C SWELL_CYC Voltage RMS_OC swell detection cycle configuration. 16 0xFFFF R/W 0x490 CFMODE CFx configuration register. 16 0x0000 R/W 0x491 COMPMODE Computation mode register. Set this register to 0x0005. 16 0x0000 R/W 0x492 ACCMODE Accumulation mode register. 16 0x0000 R/W 0x493 CONFIG3 Configuration Register 3 for configuration of power quality settings. 16 0x0000 R/W 0x494 CF1DEN CF1 denominator register. 16 0xFFFF R/W 0x495 CF2DEN CF2 denominator register. 16 0xFFFF R/W 0x498 ZXTOUT Zero-crossing timeout configuration register. 16 0xFFFF R/W 0x499 ZXTHRSH Voltage channel zero-crossing threshold register. 16 0x0009 R/W 0x49A ZX_CFG Zero-crossing detection configuration register. 16 0x0000 R/W 0x49D PHSIGN Power sign register. 16 0x0000 R 0x4A8 CRC_RSLT This register holds the CRC of the configuration registers. 16 0x0000 R 0x4A9 CRC_SPI The register holds the 16-bit CRC of the data sent out on the MOSI/RX pin during the last SPI register read. 16 0x0000 R 0x4AC LAST_DATA_16 This register holds the data read or written during the last 16-bit transaction on the SPI port. When using UART, this register holds the lower 16 bits of the last data read or write. 16 0x0000 R 0x4AE LAST_CMD This register holds the address and the read/write operation request (CMD_HDR) for the last transaction on the SPI port. 16 0x0000 R 0x4AF CONFIG2 Configuration Register 2. This register controls the high-pass filter (HPF) corner and the user period selection. 16 0x0C00 R/W |
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