ADE9153AACPZ datasheet(46/50 Pages) AD

46 / 50 page

ADE9153A

Data Sheet

Rev. 0 | Page 46 of 50

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x4AF

CONFIG2

[15:13]

Reserved

Reserved.

0x0

UPERIOD_SEL

Set this bit to use a user

configured line period, in

USER_PERIOD, for RMS_OC

calculation. If this bit is clear,

the voltage line period is

used.

0x0

R/W

[11:9]

HPF_CRN

High-pass filter corner (f3 dB)

enabled when the HPFDIS

bit in the CONFIG0 register

is equal to zero.

0x6

R/W

0 38.695 Hz.

1 19.6375 Hz.

10 9.895 Hz.

11 4.9675 Hz.

100 2.49 Hz.

101 1.2475 Hz.

110 0.625 Hz.

111 0.3125 Hz.

[8:0]

Reserved

Reserved.

0x0

0x4B0

EP_CFG

[15:8]

Reserved

Reserved.

0x0

[7:5]

NOLOAD_TMR

This register configures how

many 4 kSPS samples over

which to evaluate the no

load condition.

0x0

R/W

0 64 samples.

1 128 samples.

10 256 samples.

11 512 samples.

100 1024 samples.

101 2048 samples.

110 4096 samples.

111 Disable no load threshold.

Reserved

Reserved.

0x0

RD_RST_EN

Set this bit to enable the

energy register read with

reset feature. If this bit is set,

when one of the AWATTHR_x,

AFVARHR, or AVAHR registers

are read, it is reset and begins

accumulating energy from

zero.

0x0

R/W

EGY_LD_ACCUM

If this bit is equal to zero, the

internal energy register is

added to the user accessible

energy register. If this bit is

set, the internal energy

accessible energy register

when the EGYRDY event

occurs.

0x0

R/W

ADE9153AACPZ Datasheet(PDF) 46 Page - Analog Devices

ADE9153AACPZ Datasheet(HTML) 46 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL