ADE9153AACPZ datasheet(9/50 Pages) AD

9 / 50 page

Data Sheet

ADE9153A

Rev. 0 | Page 9 of 50

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND

DVDDOUT

CLKOUT

CLKIN

VDD

IAMS

IAN

IAP

24 VDD

23 FA0

22 FA1

21 MSH

20 DGND

19 IBMS

18 REFIN

17 AGND

ADE9153A

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE LEFT FLOATING.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 20

DGND

Digital Ground. These pins provide the ground reference for the digital circuitry in the ADE9153A and

form the return path for the Current Channel A and Current Channel B mSure currents.

DVDDOUT

1.7 V Output of the Digital LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel

with a 4.7 μF ceramic capacitor to Pin 1 (DGND). Do not connect external load circuitry to this pin.

CLKOUT

Clock Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. An external buffer

is required to drive other circuits from CLKOUT.

CLKIN

Master Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. See the

ADE9153A Technical Reference Manual for details on choosing a suitable crystal. Alternatively, an

external clock can be provided at the logic input.

5, 24

VDD

Supply Voltage. These pins provide the supply voltage for the ADE9153A. Maintain the supply voltage

at 3.3 V ± 10% for specified operation. Decouple these pins to AGND or DGND with a 4.7 μF capacitor in

parallel with a ceramic 0.1 μF capacitor.

IAMS

Output for the mSure Current Driver on Current Channel A (Phase Current Channel). IAMS is connected

to the positive end of the shunt on the phase (to the side of the shunt closest to the load, on the same

side as IAP).

7, 8

IAN, IAP

Analog Inputs for Current Channel A (Phase Current Channel). The IAP and IAN current channel is ideal

for use with shunts. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with

a maximum differential level of ±125 mV. These channels have an internal PGA gain of 16, 24, 32, and

38.4. Use these pins with the related input circuitry, as shown in Figure 37.

9, 17

AGND

Ground Reference for the Analog Circuitry. See Figure 37 for information on how to connect these

ground pins.

VDDOUT2P5

2.5 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel

with a 4.7 μF ceramic capacitor to Pin 9 (AGND). Do not connect external load circuitry to this pin.

11, 12

IBN, IBP

Analog Inputs for Current Channel B (Neutral Current Channel). The IBP and IBN current channel is ideal

for use with CTs. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a

maximum differential level of ±1000 mV. These channels have an internal PGA gain of 1, 2, or 4. Use

these pins with the related input circuitry, as shown in Figure 37.

VAMS

Path for mSure on the Voltage Channel. VAMS is connected to the bottom end of the resistor divider,

which is typically connected to the phase, as shown in Figure 1.

14, 15

VAP, VAN

Analog Inputs for the Voltage Channels. The VAP (positive) and VAN (negative) inputs are fully differential

with an input level of 0.1 V to 1.7 V. Use these pins with the related input circuitry, as shown in Figure 37.

AVDDOUT

1.9 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel

with a 4.7 μF ceramic capacitor to Pin 17 (AGND). Do not connect external load circuitry to this pin.

ADE9153AACPZ Datasheet(PDF) 9 Page - Analog Devices

ADE9153AACPZ Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL