ADE9153AACPZ datasheet(10/50 Pages) AD

10 / 50 page

ADE9153A

Data Sheet

Rev. 0 | Page 10 of 50

Pin No.

Mnemonic

Description

REFIN

Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has

a nominal value of 1.25 V. Decouple this pin to Pin 17 (AGND) with a 0.1 μF ceramic capacitor in parallel

with a 4.7 μF ceramic capacitor. After reset, the on-chip reference is enabled. An external reference

source with 1.25 V ± 0.01% can also be connected at this pin.

IBMS

Output for the mSure Current Driver on Current Channel B (Neutral Current Channel). IBMS is

connected to a wire leading through the primary winding of the CT and back to Pin 20 (DGND).

MSH

External Capacitor Pin for the mSure Current Driver. Connect an external 0.47 μF ceramic capacitor

between the MSH pin and Pin 20 (DGND).

FA1

mSure Capacitor, Positive Terminal. Connect an external capacitor of value 0.47 μF between FA0 and FA1.

FA0

mSure Capacitor, Negative Terminal. Connect an external capacitor of value 0.47 μF between FA0 and FA1.

ZX/DREADY/CF2

Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel section. This pin can be configured

to output CF2 if necessary. See the description for CF1.

CF1

Calibration Frequency (CF) Logic Outputs. The CF1 and CF2 outputs provide proportional power information

based on the CFxSEL bits in the CFMODE register. Use these outputs for operational and calibration

purposes. Scale the full-scale output frequency by writing to the CFxDEN registers, respectively.

IRQ

Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for

information about events that trigger interrupts.

RESET

Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for a minimum of 10 μs.

MOSI/RX

Data Input for the SPI Port (MOSI) and Receive Pin for the UART (RX).

MISO/TX

Data Output for the SPI Port (MISO) and Transmit Pin for the UART (TX).

SCLK

Serial Clock Input for the SPI Port. All serial data transfers are synchronized to this clock. The SCLK pin

has a Schmitt trigger input for use with a clock source that has a slow edge transition time (for example,

transitioning to opto-isolator outputs).

Slave Select for the SPI Port.

EPAD

Exposed Pad. The exposed pad must be left floating.

ADE9153AACPZ Datasheet(PDF) 10 Page - Analog Devices

ADE9153AACPZ Datasheet(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL