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ADE9153AACPZ Datasheet(PDF) 42 Page - Analog Devices |
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ADE9153AACPZ Datasheet(HTML) 42 Page - Analog Devices |
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42 / 50 page ![]() ADE9153A Data Sheet Rev. 0 | Page 42 of 50 Addr. Name Bits Bit Name Settings Description Reset Access 4 REVPCF1 Set this bit to enabled an interrupt when the CF1 polarity changed sign. 0x0 R/W 3 Reserved Reserved. 0x0 R 2 REVRPA Set this bit to enable an interrupt when the Phase A fundamental reactive power has changed sign. 0x0 R/W 1 Reserved Reserved. 0x0 R 0 REVAPA Set this bit to enable an interrupt when the Phase A total active power changes sign. 0x0 R/W 0x409 OI_LVL [31:24] Reserved Reserved. 0x0 R [23:0] OILVL_VAL Overcurrent detection threshold level. 0xFFFFFF R/W 0x40A OIA [31:24] Reserved Reserved. 0x0 R [23:0] OIA_VAL Current Channel A overcurrent RMS_OC value. If this phase is enabled with the OIA_EN bit set in the CONFIG3 register and AIRMS_OC is greater than the OILVL threshold, this value updates. 0x0 R 0x40B OIB [31:24] Reserved Reserved. 0x0 R [23:0] OIB_VAL Current Channel B overcurrent RMS_OC value. If this phase is enabled with the OIB_EN bit set in the CONFIG3 register and BIRMS_OC is greater than the OILVL threshold, this value updates. 0x0 R 0x40F VLEVEL [31:24] Reserved Reserved. 0x0 R [23:0] VLEVEL_VAL This register is used in the algorithm that computes the fundamental reactive power. 0x45D450 R/W 0x411 DIPA [31:24] R eserved Reserved. 0x0 R [23:0] DIPA_VAL Voltage channel RMS_OC value during a dip condition. 0x7FFFFF R 0x415 SWELLA [31:24] R eserved Reserved. 0x0 R [23:0] SWELLA_VAL Voltage channel RMS_OC value during a swell condition. 0x0 R 0x41F PHNOLOAD [31:3] R eserved Reserved. 0x0 R 2 AFVARNL This bit is set if the Phase A fundamental reactive energy is in no load. 0x0 R/W 1 AVANL This bit is set if the Phase A total apparent energy is in no load. 0x0 R/W 0 AWATTNL This bit is set if the Phase A total active energy is in no load. 0x0 R/W |
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