AS5013 datasheet(17/50 Pages) AMSCO

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[v2-00] 2021-Apr-19

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AS5013 − Detailed Description

The AS5013 operates as a slave on the I²C bus. Connections to

the bus are made through the open-drain I/O lines SDA and the

input SCL. Clock stretching is not included.

Automatic Increment of Address Pointer

The AS5013 slave automatically increments the address pointer

after each byte transferred. The increase of the address pointer

is independent from the address being valid or not.

Invalid Addresses

If the user sets the address pointer to an invalid address, the

address byte is not acknowledged. Nevertheless a read or write

cycle is possible. The address pointer is increased after each

byte.

Reading

When reading from a wrong address, the AS5013 slave data

returns all zero. The address pointer is increased after each byte.

Sequential read over the whole address range is possible

including address overflow.

Writing

A write to a wrong address is not acknowledged by the AS5013

slave, although the address pointer is increased. When the

address pointer points to a valid address again, a successful

write access is acknowledged. Page write over the whole

address range is possible including address overflow.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as start or stop

signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy:

Both data and clock lines remain HIGH.

Start Data Transfer:

A change in the state of the data line, from HIGH to LOW, while

the clock is HIGH, defines a START condition.

Stop Data Transfer:

A change in the state of the data line, from LOW to HIGH, while

the clock line is HIGH, defines the STOP condition.

Data Valid:

The state of the data line represents valid data when, after a

START condition, the data line is stable for the duration of the

HIGH period of the clock signal. The data on the line must be

changed during the LOW period of the clock signal. There is one

clock pulse per bit of data. Each data transfer is initiated with a

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