ASL1507SHN datasheet(35/56 Pages) NXP

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NXP Semiconductors

ASL1507SHN; ASL2507SHN

Single-phase and two-phase boost converter with limp-home mode

ASL1507_ASL2507

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Product data sheet

Rev. 1 — 26 April 2018

35 / 56

8.13.3 NVM register map

The ASL1507SHN; ASL2507SHN allows limp-home values during NVM access.

Table 47 shows the linking of the NVM addresses to the register addresses.

Table 47. Mapping of NVM registers to control registers

NVM address linked to

SPI register 36h[4:0]

NVM_DATA[15:8] linked to

SPI register 37h and 59h

NVM_DATA[7:0] linked to

SPI register 38h and 5Ah

00h

n.a.

multi-content NVM data fields

01h

NVM write count bit 15 to bit 8

NVM write count bit 7 to bit 0

02h

n.a.

function control

03h

n.a.

gate driver enable

04h

gate driver output

output voltage 1

05h

output voltage 2

limit voltage output 1

06h

limit voltage output 2

maximum coil current VO1

07h

maximum coil current VO2

clock divider for VO1

08h

clock divider for VO2

SS scenario logic 1

09h

SS scenario logic 2

phase‑off time and phase delay of

output 1

0Ah

phase‑off time and phase delay of

output 2

gate driver phase

0Bh

phase select configuration

loop filter proportional configuration

0Ch

loop filter integral configuration

slope compensation configuration

0Dh

current sense slope resistor

configuration

VGG control

0Eh

internal 1

overvoltage threshold

0Fh

undervoltage threshold

spread spectrum enable

10h

internal 2

internal 3

11h

internal 4

internal 5

12h

ramp up output 1

ramp up output 2

The NVM data fields that contain more than just one register are shown in Table 48.

Table 48. Overview of multi-content NVM data field

NVM

address

Name 7 6 5

00h

enable VGG

voltage range

to 16 V

AUTO LIMP_DIS customer write pattern to indicate that NVM is

programmed:

00 is not programmed (internal defaults are used)

01 is programmed

10 is programmed

11 is not programmed (internal defaults are used)

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