ADFS5758 datasheet(41/75 Pages) AD

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Data Sheet

ADFS5758

Rev. 0 | Page 41 of 75

VIOUT

INTERFACE LOGIC

OUTPUT

AMPLIFIER

SDO

SDI

16-BIT

DAC

REFIN

SYNC

LDAC

(HARDWARE OR SOFTWARE)

DAC INPUT

USER

GAIN AND OFFSET

CALIBRATION

SCLK

DAC OUTPUT

(READ ONLY)

CLEAR CODE

CLEAR EVENT

(WDT TIMEOUT)

Figure 83. Simplified Serial Interface of Input Loading Circuitry

DAC Data Integrity Diagnostics

To protect against transient changes to the internal digital

circuitry, the digital block stores both the digital DAC value

and an inverted copy of the digital DAC value. A check is

completed to ensure that the two values correspond to each

other before the DAC is strobed to update to the DAC code.

This feature is enabled by default (INVERSE_DAC_CHECK_

EN bit in the DIGITAL_DIAG_CONFIG register).

Another optional diagnostic feature is the internal dual calibration

feature. This feature is enabled by setting the DUAL_CAL_EN

bit in the DIGITAL_DIAG_CONFIG register. When enabled,

the internal calibration on the 16-bit user DAC code is completed

twice. The DAC is only updated when both results match. If a

fail is registered, no DAC write occurs and the DUAL_CAL_

ERR flag is set.

Outside of the digital block, the DAC code is stored in latches

(as shown in Figure 84). These latches are potentially

vulnerable to the same transient events as those protected

against within the digital block. To protect the DAC latches

against such transients, the DAC latch monitor feature can be

enabled via the DAC_LATCH_MON_EN bit within the

DIGITAL_DIAG_CONFIG register. This feature monitors the

actual digital code driving the DAC and compares it with the

digital code generated within the digital block. Any difference

between the two codes causes the DAC_LATCH_MON_ERR flag

to be set in the DIGITAL_DIAG_RESULTS register.

16-BIT

DAC

DIGITAL

BLOCK

DAC LATCHES

Figure 84. DAC Data Integrity

LOCKABLE USER CONFIGURATION SPACE

The ADFS5758 user configuration resisters listed in Table 16

have the feature of being lockable as read only. This means that

if locked, any writes to these registers are ignored and flagged in

the DIGITAL_DIAG_RESULTS register via the CFG_LOCK_

CHECK_ERR bit (if enabled) and via the FAULT pin.

Note that the VLDO external capacitor detection feature must

not be enabled prior to locking the configuration register space

because this is a self clearing bit and causes the CFG_LOCK_

CHECK_ERR bit to flag if the corresponding value changes

subsequent to locking the configuration register space.

The user must write Data 0x4765 to the key register to lock the

registers. To unlock the registers, two unlock keys must be

written to the key register. The first key is Data 0x896D, and the

second key is Data 0x57AB. The unlock keys must be written to

the key register in that order.

The CFG_LOCK_CHECK_EN bit in the DIGITAL_DIAG_

CONFIG register must be set to enable flagging of an attempt

to write to a locked register via the CFG_LOCK_CHECK_ERR bit

in the DIGITAL_DIAG_RESULTS register. If the CFG_LOCK_

CHECK_EN bit is not set, the user has no indication that a

write was attempted to the locked registers.

Table 16. Lockable Registers

Address

0x03

CLEAR_CODE

0x04

USER_GAIN

0x05

USER_OFFSET

0x06

DAC_CONFIG

0x09

GP_CONFIG1

0x0A

GP_CONFIG2

0x0B

DCDC_CONFIG1

0x0C

DCDC_CONFIG2

0x0F

WDT_CONFIG

0x10

DIGITAL_DIAG_CONFIG

0x11

ADC_CONFIG

0x12

FAULT_PIN_CONFIG

ADFS5758 Datasheet(PDF) 41 Page - Analog Devices

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