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ADFS5758 Datasheet(PDF) 68 Page - Analog Devices

Part # ADFS5758
Description  Single-Channel, 16-Bit, Current/Voltage Output DAC, Functional Safety Approved for Unipolar Current Output
PDF  75 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADFS5758 Datasheet(HTML) 68 Page - Analog Devices

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ADFS5758
Data Sheet
Rev. 0 | Page 68 of 75
Bits
Bit Name
Description
Reset
Access
FAULT pin.
3
IOUT_OC_ERR
If this bit is set, do not map the current output open-circuit error flag to the FAULT pin.
0x0
R/W
2
VOUT_SC_ERR
If this bit is set, do not map the voltage output short-circuit error flag to the FAULT pin.
0x0
R/W
1
DCDC_DIE_TEMP_ERR
If this bit is set, do not map the dc-to-dc die temperature error flag to the FAULT pin.
0x0
R/W
0
MAIN_DIE_TEMP_ERR
If this bit is set, do not map the main die temperature error flag to the FAULT pin.
0x0
R/W
Two Stage Readback Select Register
Address: 0x13, Reset: 0x130000, Name: TWO_STAGE_READBACK_SELECT
This register selects the address of the register required for a two stage readback operation. The address of the register selected for
readback is stored in Bits[D4:D0].
Table 45. Bit Descriptions for TWO_STAGE_READBACK_SELECT
Bits
Bit Name
Description
Reset
Access
21
FAULT_PIN_STATUS
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
0x0
R
[20:16]
REGISTER_ADDRESS
Register address.
0x0
R
[15:7]
Reserved
Reserved.
0x0
R
[6:5]
READBACK_MODE
These bits control the SPI readback mode.
0x0
R/W
0: two stage SPI readback mode (default).
01: autostatus readback mode: the status register contents are shifted out on SDO for
every SPI frame.
10: shared SYNC autostatus readback mode. This mode allows the use of a shared SYNC
line on multiple devices (distinguished using the hardware address pins). After each valid
write to a device, a flag is set. This mode behaves similar to the normal autostatus read-
back mode, except that the device does not output the status register contents on SDO
as SYNC goes low, unless the internal flag is set (that is, the previous SPI write is valid).
11: the status register contents and the previous SPI frame instruction are alternately
available on SDO.
[4:0]
READBACK_SELECT
Select readback address for a two stage readback.
0x0
R/W
0x00: NOP register (default).
0x01: DAC_INPUT register.
0x02: DAC_OUTPUT register.
0x03: CLEAR_CODE register.
0x04: USER_GAIN register.
0x05: USER_OFFSET register.
0x06: DAC_CONFIG register.
0x07: SW_LDAC register.
0x08: key register.
0x09: GP_CONFIG1 register.
0x0A: GP_CONFIG2 register.
0x0B: DCDC_CONFIG1 register.
0x0C: DCDC_CONFIG2 register.
0x0D: reserved (do not select this option).
0x0E: reserved (do not select this option).
0x0F: WDT_CONFIG register.
0x10: DIGITAL_DIAG_CONFIG register.
0x11: ADC_CONFIG register.
0x12: FAULT_PIN_CONFIG register.
0x13: TWO_STAGE_READBACK_SELECT register.
0x14: DIGITAL_DIAG_RESULTS register.
0x15: ANALOG_DIAG_RESULTS register.
0x16: status register.
0x17: CHIP_ID register.



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