STLC4420A datasheet(24/40 Pages) STMICROELECTRONICS

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Serial host interface

STLC4420A

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4.3

AHB masters

The DMA engines are contained within the Serial Host interface. The DMA engines access

data on the device via a pair of AHB masters. AHB1 is connected to the standard AHB bus

which is shared with the CPU and DMA controller AHB masters.

The Serial Host has a second AHB master connected to the AHB Ram directly via a AHB2.

The Serial Host AHB2 master and the AHB Ram AHB2 slave are the only master and slave

on the AHB2 bus. This guarantees sufficient bandwidth for the serial host interface.

When the AHB master is accessing APB registers the ApbAccess bit must be set to force

the master to use word (32-bit) transfers so that the APB registers are not set to an

indeterminate state by a pair of half-word (16-bit) transfers.

DMA read data is prefetched when the DMA Read Address is written and the DMA Write

Enable is asserted. The host must not read DMA Data register before the prefetch

completes. There must be 20 ABClock cycles between the end the Data Phase when DMA

Read Address is written and the end of Address Phase which selects the DMA Read

Figure 14.

3-WireInvWait1

Figure 15.

3-WireShiftWait1

Figure 16.

3-WireInvShftWait1

STLC4420A Datasheet(PDF) 24 Page - STMicroelectronics