STLC4420A datasheet(32/40 Pages) STMICROELECTRONICS

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Registers description

STLC4420A

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5.5

Host interrupt enable register

The Host writes this 32-bit register to enable interrupts from the host interrupt register. A

Host interrupt is generated if the corresponding bit in both the host interrupt register and the

host interrupt enable register are both active.

The format of the register is defined in Table 11.

5.6

Host interrupt acknowledge register

This 32-bit register is written by the Host, and clears interrupts in the Host Interrupt Register.

Writing a logic 1 in any bit position cause the corresponding interrupt bit to be cleared. All

other bits are unaffected.

The format of the register is defined in Table 12.

26:16

Reserved

Not Implemented

15:0

ARMMSG

General purpose Host Message Interrupts. Written by the ARM

to enable Interrupt on selected bit(s)

Table 10.

Host interrupt register

Bit position

Name

Description

Table 11.

Host interrupt enable register

Bit position

Name

Description

ARM_ASLEEP

Indicates that an access to hardware registers or device memory

(by Host) was attempted while the device was in sleep-mode.

DMA wr done

DMA rd done

DMA rd ready

NotSleep

26:16

Reserved

Not Implemented

15:0

HOSTMSG

General purpose ARM Message Interrupts. Written by the ARM

to cause an interrupt to the HOST

Table 12.

Host interrupt acknowledge register

Bit position

Name

Description

ARM_ASLEEP

Indicates that an access to hardware registers or device memory

(by Host) was attempted while the device was in sleep-mode.

DMA WR done

Last write occurred

DMA RD done

Last read occurred

DMA RD ready

DMA RD FIFO ready to be read

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