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GS9002A PIN DESCRIPTIONS

PIN NO.

SYMBOL

TYPE

DESCRIPTION

1

Power Supply: Most negative power supply connection.

2

Power Supply: Most positive power supply connection for the PLL and scrambler.

3

SYNC DET.

O

TTL output level that detects the occurrence of all zero’s or all one’s at inputs PD2-PD9

and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words

(000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or

High when PD2 - PD9 are Low or High respectively.

4

Power Supply: Most negative power supply connection.

Power Supply: Most positive power supply connection for the input data latches and serializer.

6

SYNC DET.

I

TTL level input that disables the internal Sync Detector when HIGH. This allows the

DISABLE

GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data.

7-16

PD0-PD9

I

TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB.

17

PCK-IN

I

TTL level input of the Parallel Clock.

18

Power Supply: Most negative power supply connection.

19

PCK OUT

O

Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the

internal VCO. The VCO is divided by 10 in order to produce this output.

20

LOCK DET.

O

TTL level output which goes HIGH when the internal PLL is locked.

21

Power Supply: Most positive power supply connection for the PLL and scrambler.

22

LOOP FILT.

I

Connection for the R-C loop filter components. The loop filter sets the PLL loop

parameters.

23

Power Supply: Most negative power supply connection.

24

NC

25

Power Supply: Most negative power supply connection.

26

SSS

I

Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when

logic LOW or direct serializer output when logic HIGH.

27

Power Supply: Most negative power supply connection.

28

Power Supply: Most positive power supply connection for the PLL and scrambler.

29

I

Compensation RC network for internal voltage regulator that requires decoupling with a series

0.1µF capacitor and 820

Ω resistor. Components should be located as close as possible to the pin.

30

Power Supply: Most negative power supply connection.

31

I

VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when

the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is

32

I

VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when

the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35)

33

I

VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when

the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35)

34

I

VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when

the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is

35,36

DRS0, 1

I

TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency