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L9300 Datasheet(PDF) 101 Page - STMicroelectronics |
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L9300 Datasheet(HTML) 101 Page - STMicroelectronics |
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101 / 182 page ![]() Symbol Parameter Test condition Min Typ Max Unit Pin AC Parameters fop Transfer Frequency Design Information 6 MHz SCLK tsclk SCLK Period (2) Design Information 167 ns SCLK tlead Enable Lead Time (3) Design Information 750 ns SCLK tlag Enable Lag Time (4) Design Information 100 ns SCLK, CS tsclkhs SCLK High Time (5) Design Information 75 ns SCLK tsclkls SCLK Low Time (6) Design Information 75 ns SCLK tsus MOSI Input Setup Time (7) Design Information 30 ns SDI ths MOSI Input Hold Time (8) Design Information 30 ns SDI ta MISO Access Time (9) Design Information 50pF load 100 ns SDO tdis MISO Disable Time (10) Design Information 50pF load 100 ns SDO tvs MISO Output Valid Time (11) Design Information 50pF load 70 ns SDO tho MISO Output Hold Time (12) Design Information 50pF load 10 ns SDO tr MISO Rise Time (13) Design Information 50pF load 50 ns SDO tf MISO Fall Time (14) Design Information 50pF load 50 ns SDO tcsn CS Negated Time (15) Design Information 750 ns CS tsh SCLK Hold Time (16) Design Information 100 ns SCLK teof End of frame time Time from CS rising edge to internal registers update Design Information 1/ fOSCINT 2/fOSCINT ns CS Figure 63. SPI timing CS SCLK 3 9 5 7 8 6 11 2 MSB OUT 4 15 13 12 10 LSB IN DATA DATA LSB OUT DON’T CARE MSB IN MISO MOSI GADG0708171624PS L9300 SPI electrical characteristics DS12258 - Rev 4 page 101/182 |
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