L9300 datasheet(26/182 Pages) STMICROELECTRONICS

26 / 182 page

8.2.3

VDD2 error handling

Table 9. VDD2 type of errors

Type of error

Detection

condition

Action

Clear SPI

flag

Restart condition

VDD2 out of regulation

ON state

Set VDD2_OUT_OF_REGULATION SPI flag (4) in TRK-CAN

FAULT register

On read

N.A

VDD2 reverse current

ON state

VDD2 internal path to VDD2_SUP open,

VDD2_REVERSE_CURRENT SPI flag (6) latched in TRK-

CANFAULT register

On read

Automatic restart

when fault

disappears.

VDD2 overtemperature

ON state

No action if out of regulation is not triggered; output disabled,

and T_SD_TRK (5)SPI fault bit latched otherwise in TRK-CAN

FAULT register

On read

Automatic restart

with slope control

after OT fault

disappears.

8.3

VDD3

8.3.1

VDD3 functional description

VDD3 is a linear regulator using external N-channel transistor as output stage to deliver current to the load and

reduce ASIC power dissipation. The regulated voltage is configurable through the external feedback resistors.

Dedicated monitors are present on the VDD3_SEL pin to detect VDD3 undervoltage and overvoltage conditions;

voltage monitors are not masked during power-up phase.

Figure 12. VDD3 linear regulator with external N-ch FET

VCP

Driver

loop

Control

Linear

VDD3

R3dw

R3up

VDRAIN

VDD3_SEL

VDD3

VDD3_G

GADG1007171200PS

VDRAIN can be connected to either VBATP or, in order to limit power consumption, to a pre-regulated voltage.

8.3.2

VDD3 electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VDRAIN ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noticed. All voltages refer

to GND pin. STD20NF06L used as test reference for external MOS.

L9300

VDD3

DS12258 - Rev 4

page 26/182

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