L9788 datasheet(54/264 Pages) STMICROELECTRONICS

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Watchdog

L9788

54/264

DS12308 Rev 4

4.1.7

Access during a sequencer-run

A sequencer-run (which means the same as a monitoring cycle) is initiated by the writing of

a response (i.e. all answer bytes <RESP_BYTE3..0>) or a write to <RESPTIME> or by

reaching "end of time window". It's not interrupted by a new access, i.e. the monitoring

module completes the action already started:



A sequencer-run was initiated by a "response write": The sequencer completes its task

with the data of the previous access and the new data are ignored.



A sequencer-run was initiated by a "response-time write": The sequencer uses the

response-time of the previous access, the error counter is correspondingly

incremented by one and the <CHRT> bit (REQUHI register) is set and the new data are

ignored. <CHRT> will be reset by reading and by the next start of a sequencer run (not

reset by the sequencer run that is started by a "response-time write")



A sequencer-run was initiated by "end of time window": The sequencer finishes the

started run, the error counter is incremented by one and the new data are ignored.

The writing of a response-time during a sequencer-run will not set the <CHRT> bit (REQUHI

At the end of the sequencer run W_RESP bit is set to 0 if the response is correct, it is set to

1 if the response is incorrect.

4.1.8

Clock and time references

The monitoring module works independently by the micro-controller clock so that it can

monitor the timing of the micro-controller.

This oscillator is integrated in the U-chip and it provides a clock CLK1 for the monitoring

module.

Clocked with CLK1, a divider generates the base time of 1.6 ms @ 64 kHz for the response-

time and 8*1.6 ms = 12.8 ms @ 64 kHz for the fixed time window. Accuracy of CLK1 is ±

5%.

The response-time is adjustable by the controller in the range 0ms to about 100ms (register

RESPTIME).

The response-time can be calculated with the equation

Response_Time = RESPTIME [5:0]) *1.6 ms

If 39 kHz clock is selected by wda_win_sel configuration bit, the base time changes

becoming 2.6ms @ 39 kHz. This implies the change of all related timing values: 8*2.6 ms =

20.8 ms @ 39 kHz for the fixed time window and response time becomes RESPTIME [5:0]

*2.6 ms.

The WDA_RESPTIME (CONFIG_REG9_0) register is set to '0011 1111'b after a reset. The

ERROR COUNTER is incremented by one if the controller changes the response-time. If

the response-time is set to 0 ms, then the ERROR COUNTER is incremented by one even if

a correct response is received within the time window. The maximum error reaction time is

given by: maximum response-time, response at the end of a time-window and ERROR

COUNTER 0 Is 5 *(100.8 ms + 12.8 ms) = 568 ms.

In order to assure correct response write, there must be a minimum distance between 2

consecutive writes equal to 5us, this time does not depend on WDA_WIN_SEL

(CONFIG_REG9_1 D2).

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