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CS47L35 Datasheet(PDF) 228 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 228 Page - Cirrus Logic

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DS1085F3
CS47L35
5 Applications
5 Applications
5.1 Recommended External Components
This section provides information on the recommended external components for use with the CS47L35.
5.1.1
Analog Input Paths
The CS47L35 supports up to six analog audio input connections. Each of these inputs is biased to the internal DC
reference, VREF. (Note that this reference voltage is present on the VREFC pin.) A DC-blocking capacitor is required for
each analog input pin used in the target application. The choice of capacitor is determined by the filter that is formed
between that capacitor and the impedance of the input pin. The circuit is shown in Fig. 5-1.
Figure 5-1. Audio Input Path DC-Blocking Capacitor
In accordance with the CS47L35 input pin resistance (see Table 3-5), a 1-
F capacitance for all input connections gives
good results in most cases, with a 3-dB cut-off frequency around 13 Hz.
Ceramic capacitors are suitable, but take care to ensure the desired capacitance is maintained at the AVDD operating
voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to
electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required.
A single capacitor is required for a single-ended line or microphone input connection. For a differential input connection,
a DC-blocking capacitor is required on both input pins.
The external connections for single-ended and differential microphones, incorporating the CS47L35 microphone bias
circuit, are shown in Section 5.1.3; see Fig. 5-2.
5.1.2
DMIC Input Paths
The CS47L35 supports up to four channels of DMIC input; two channels of audio data can be multiplexed on each
DMICDATn pin. Each of these stereo pairs is clocked using the respective DMICCLKn pin.
Table 4-118. Device Reset and ID
Register Address
Bit
Label
Default
Description
R0 (0x0000)
Software_Reset
15:0 SW_RST_DEV_
ID[15:0]
0x6360 Writing to this register resets all registers to their default state.
Reading from this register indicates Device ID 0x6360.
R1 (0x0001)
Hardware_
Revision
7:0
HW_
REVISION[7:0]
—
Hardware Device revision. This field is incremented for every new revision of the
device.
R2 (0x0002)
Software_Revision
7:0
SW_
REVISION[7:0]
—
Software Device revision. This field is incremented if software driver compatibility or
software feature support is changed.
Fc
= High-pass 3 dB cut-off frequency
Fc
=
1
2 RC
Input
C
R
VREF
PGA
+
–



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