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CS47L35 Datasheet(PDF) 225 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 225 Page - Cirrus Logic

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DS1085F3
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CS47L35
4.22 Power-On Reset (POR)
4.22.1 Boot Sequence
Following power-on reset, a boot sequence is executed. The BOOT_DONE_STSx bits are asserted on completion of the
boot sequence, as described in Table 4-115. Control-register writes should not be attempted until BOOT_DONE_STSx
has been asserted. Note that the BOOT_DONE_STS1 and BOOT_DONE_STS2 bits provide the same information.
The BOOT_DONE_STSx signal is an input to the interrupt control circuit and can be used to trigger an interrupt event on
completion of the boot sequence; see Section 4.15. Under default register conditions, a falling edge on the IRQ pin
indicates completion of the boot sequence.
For details of the boot sequence, see Section 4.18.
4.22.2 Digital I/O Status in Reset
Table 4-116 describes the default status of the CS47L35 digital I/O pins on completion of power-on reset and before any
register writes. The same default conditions are also applicable on completion of a hardware reset or software reset (see
Section 4.23).
The same default conditions are applicable following a wake-up transition, except for the IRQ and RESET pins. These are
always-on pins whose configuration is unchanged in Sleep Mode and during a wake-up transition.
Note that the default conditions described in Table 4-116 are not valid if modified by the boot sequence or by a wake-up
control sequence. See Section 4.18 for details of these functions.
Table 4-115. Device Boot-Up Status
Register Address Bit
Label
Default
Description
R6272 (0x1880)
IRQ1_Raw_
Status_1
7 BOOT_DONE_
STS1
0
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot Sequence has completed.
R6528 (0x1980)
IRQ2_Raw_
Status_1
7 BOOT_DONE_
STS2
0
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot Sequence has completed.
Table 4-116. CS47L35 Digital I/O Status in Reset
Power Domain
Pin No
Name
Type
Reset Status
MICVDD 1
E3
IN1ALN/DMICCLK1
Analog input/Digital output
Analog input
C1
IN1ARN/DMICDAT1
Analog input/Digital input
Analog input
H4
IN2LN/DMICCLK2
Analog input/Digital output
Analog input
E1
IN2RN/DMICDAT2
Analog input/Digital input
Analog input
DBVDD1
T12
AIF1BCLK/GPIO9
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
R11
AIF1LRCLK/GPIO11
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
P10
AIF1RXDAT/GPIO8
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
T10
AIF1TXDAT/GPIO10
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
M10
CIF1MISO
Digital output
Digital output
L9
CIF1MOSI
Digital input
Digital input
L11
CIF1SCLK
Digital input
Digital input
K10
CIF1SS
Digital input
Digital input
P12
CIF2SCLK
Digital input
Digital input
N11
CIF2SDA
Digital I/O
Digital input
J9
IRQ
Digital output
Digital output
M12
MCLK1
Digital input
Digital input
T8
MIF1SCLK/GPIO16
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
P8
MIF1SDA/GPIO7
Digital I/O
Digital input (GPIO), bus-keeper enabled 2
H8
RESET
Digital input
Digital input, Pull-up to DBVDD1
R9
SLIMCLK
Digital I/O
Digital input
N9
SLIMDAT
Digital I/O
Digital input



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