CS47L35 datasheet(227/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.23 Hardware Reset, Software Reset, Wake-Up, and Device ID

4.23.2 Software Reset

A software reset is executed by writing any value to register R0. A software reset causes most of the CS47L35 control

registers to be reset to their default states. Note that the control-write sequencer memory is retained during software reset.

Note that the first register read/write operation following a software reset may be unsuccessful, if the register access is

attempted via a different control interface to the one that commanded the software reset. Note that only the first register

read/write is affected, and only when using more than one control interface.

4.23.3 Wake-Up

The CS47L35 is in Sleep Mode when AVDD and DBVDD1 are present, and DCVDD is below its reset threshold. (Note

that specific control requirements are also applicable for entering Sleep Mode, as described in Section 4.13.)

In Sleep Mode, most of the digital core (and control registers) are held in reset; selected functions and control registers

are maintained via an always-on internal supply domain. See Section 4.13 for details of the always-on functions.

A wake-up transition (from Sleep Mode) is similar to a software reset, but selected functions and control registers are

maintained via an always-on internal supply domain—the always-on registers are not reset during wake-up. See

Section 4.13 for details of the always-on functions.

4.23.4 Write Sequencer and DSP Firmware Memory Control in Reset and Wake-Up

The control-write sequencer memory contents reverts to its default contents following power-on reset, a hardware reset,

or a Sleep Mode transition. The control sequences (including any user-defined sequences) are maintained in the

sequencer memory through software reset.

The DSP firmware memory contents are cleared following power-on reset, a hardware reset, or a Sleep Mode transition.

The firmware memory contents are not affected by software reset, provided DCVDD is held above its reset threshold.

See Section 5.2 for a summary of the CS47L35 memory reset conditions.

4.23.5 Boot Sequence

Following hardware reset, software reset, or wake-up from Sleep Mode, a boot sequence is executed. The BOOT_DONE_

STSx bits (see Table 4-115) are deasserted during hardware reset and software reset, and also in Sleep Mode. The

BOOT_DONE_STSx bits are asserted on completion of the boot sequence. Control register writes should not be

attempted until BOOT_DONE_STSx has been asserted.

The BOOT_DONE_STSx status is an input to the interrupt control circuit and can be used to trigger an interrupt event; see

Section 4.15. Note that the BOOT_DONE_STS1 and BOOT_DONE_STS2 bits provide the same information.

For details of the boot sequence, see Section 4.18.

4.23.6 Digital I/O Status in Reset

The status of the CS47L35 digital I/O pins following hardware reset, software reset, or wake-up is described in

Section 4.22.2.

4.23.7 Device ID

The device ID can be read from Register R0. The hardware revision can be read from Register R1.

The software revision can be read from Register R2. The software revision code is incremented if software driver

compatibility or software feature support is changed.

CS47L35 Datasheet(PDF) 227 Page - Cirrus Logic