STM32W108HB datasheet(122/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.6.4

DMA

The DMA Channels section describes how to configure and use the serial receive and

transmit DMA channels.

The receive DMA channel has special provisions to record UART receive errors. When the

DMA channel transfers a character from the receive FIFO to a buffer in memory, it checks

the stored parity and frame error status flags. When an error is flagged, the

SC1_DMARXERRAR/SC1_DMARXERRBR register is updated, marking the offset to the

first received character with a parity or frame error. Similarly if a receive overrun error

occurs, the SC1_DMARXERRAR/SC1_DMARXERRBR registers mark the error offset. The

receive FIFO hardware generates the OVR interrupt and DMA status register indicates the

error immediately, but in this case the error offset is 4 characters ahead of the actual

overflow at the input to the receive FIFO. Two conditions will clear the error indication:

setting the appropriate RXRST bit in the SC1_DMACR register, or loading the appropriate

DMA buffer after it has unloaded.

9.6.5

Interrupts

UART interrupts are generated on the following events:

●

Transmit FIFO empty and last character shifted out (depending on SCx_ICR, either the

0 to 1 transition or the high level of SC1_UARTTXIDLE)

●

Transmit FIFO changed from full to not full (depending on SCx_ICR, either the 0 to 1

transition or the high level of SC1_UARTTXFREE)

●

Receive FIFO changed from empty to not empty (depending on SCx_ICR, either the 0

to 1 transition or the high level of SC1_UARTRXVAL)

●

Transmit DMA buffer A/B complete (1 to 0 transition of TXAACK/TXBACK)

●

Receive DMA buffer A/B complete (1 to 0 transition of RXAACK/RXBACK)

●

Character received with parity error

●

Character received with frame error

●

Character received and lost when receive FIFO was full (receive overrun error)

To enable CPU interrupts, set the desired interrupt bits in the second level SCx_IER register.

9.7

Direct memory access (DMA) channels

The STM32W108 serial DMA channels enable efficient, high-speed operation of the SPI

and UART controllers by reducing the load on the CPU as well as decreasing the frequency

of interrupts that it must service. The transmit and receive DMA channels can transfer data

between the transmit and receive FIFOs and the DMA buffers in main memory as quickly as

it can be transmitted or received. Once software defines, configures, and activates the DMA,

it only needs to handle an interrupt when a transmit buffer has been emptied or a receive

buffer has been filled. The DMA channels each support two memory buffers, labeled A and

B, and can alternate ("ping-pong") between them automatically to allow continuous

communication without critical interrupt timing.

STM32W108HB Datasheet(PDF) 122 Page - STMicroelectronics

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