STM32W108HB datasheet(119/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Serial interfaces

Doc ID 16252 Rev 14

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9.6.1

Setup and configuration

The UART baud rate clock is produced by a programmable baud generator starting from the

24 Hz clock:

MHz

baud

The integer portion of the divisor, N, is written to the SC1_UARTBRR1 register and the

fractional part, F, to the SC1_UARTBRR2 register. Table 29 shows the values used to

generate some common baud rates and their associated clock frequency error. The UART

requires an internal clock that is at least eight times the baud rate clock, so the minimum

allowable setting for SC1_UARTBRR1 is ‘8’.

Note:

The UART may receive corrupt bytes if the interbyte gap is long or there is a baud rate

mismatch between receive and transmit. The UART may detect a parity and/or framing error

on the corrupt byte, but there will not necessarily be any error detected. As a result, the

device should be operated in systems where the other side of the communication link also

uses a crystal as its timing reference, and baud rates should be selected to minimize the

baud rate mismatch to the crystal tolerance. UART protocols should contain some form of

error checking (e.g. CRC) at the packet level to detect, and retry in the event of errors.

The UART character frame format is determined by three bits in the SC1_UARTCR register:

●

STOP selects the number of stop bits in transmitted characters. (Only one stop bit is

ever required in received characters.) If this bit is clear, characters are transmitted with

one stop bit; if set, characters are transmitted with two stop bits.

●

PCE controls whether or not received and transmitted characters include a parity bit. If

PCE is clear, characters do not contain a parity bit, otherwise, characters do contain a

parity bit.

●

PS specifies whether transmitted and received parity bits contain odd or even parity. If

this bit is clear, the parity bit is even, and if set, the parity bit is odd. Even parity is the

exclusive-or of all of the data bits, and odd parity is the inverse of the even parity value.

PS has no effect if PCE is clear.

Table 29.

UART baud rate divisors for common baud rates

Baud rate (bits/sec)

SC1_UARTBRR1

SC1_UARTBRR2

Baud rate error (%)

300

40000

2400

5000

4800

2500

9600

1250

19200

625

38400

312

57600

208

- 0.08

115200

104

+ 0.16

230400

+ 0.16

460800

+ 0.16

921600

+ 0.16

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