STM32W108HB datasheet(123/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Serial interfaces

Doc ID 16252 Rev 14

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Note:

DMA memory buffer terminology:

●

load - make a buffer available for the DMA channel to use

●

pending - a buffer loaded but not yet active

●

active - the buffer that will be used for the next DMA transfer

●

unload - DMA channel action when it has finished with a buffer

●

idle - a buffer that has not been loaded, or has been unloaded

To use a DMA channel, software should follow these steps:

●

Reset the DMA channel by setting the TXRST (or RXRST) bit in the SCx_DMACR

●

Set up the DMA buffers. The two DMA buffers, A and B, are defined by writing the start

address to SCx_DMATXBEGADDAR/SCx_DMATXBEGADDBR (or

SCx_DMARXBEGADDAR/SCx_DMARXBEGADDBR) and the (inclusive) end address

to SCx_DMATXENDADDAR/SCx_DMATXENDADDBR (or

SCx_DMARXENDADDAR/SCx_DMARXENDADDBR). Note that DMA buffers must be

in RAM.

●

Configure and initialize SCx for the desired operating mode.

●

Enable second level interrupts triggered when DMA buffers unload by setting the

TXULODA/B (or RXULODA/B) bits in the SCx_ISR register.

●

Start the DMA by loading the DMA buffers by setting the TXLODA/TXLODB (or

RXLODA/RXLODB) bits in the SCx_DMACR register.

A DMA buffer's end address, SCx_DMATXENDADDAR/SCx_DMATXENDADDBR (or

SCx_DMARXENDADDAR/SCx_DMARXENDADDBR), can be written while the buffer is

loaded or active. This is useful for receiving messages that contain an initial byte count,

since it allows software to set the buffer end address at the last byte of the message.

As the DMA channel transfers data between the transmit or receive FIFO and a memory

buffer, the DMA count register contains the byte offset from the start of the buffer to the

address of the next byte that will be written or read. A transmit DMA channel has a single

DMA count register (SCx_DMATXCNTR) that applies to whichever transmit buffer is active,

but a receive DMA channel has two DMA count registers

(SCx_DMARXCNTAR/SCx_DMARXCNTBR), one for each receive buffer. The DMA count

the transmit DMA count, is loaded, or until the DMA is reset.

The receive DMA count register may be written while the corresponding buffer is loaded. If

the buffer is not loaded, writing the DMA count register also loads the buffer while

preserving the count value written. This feature can simplify handling UART receive errors.

The DMA channel stops using a buffer and unloads it when the following is true:

(DMA buffer start address + DMA buffer count) > DMA buffer end address

Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is

unloaded after it is filled with data, but writing to the buffer end address or buffer count

registers can also cause a buffer to unload early.

Serial controller DMA channels include additional features specific to the SPI and UART

operation and are described in those sections.

STM32W108HB Datasheet(PDF) 123 Page - STMicroelectronics

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