STM32W108HB datasheet(206/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Bit 11 OC4PE: Output Compare 4 Preload Enable

0: Buffer register for TIMx_CCR4 is disabled. TIMx_CCR4 can be written at anytime, the new

value is used by the shadow register immediately.

1: Buffer register for TIMx_CCR4 is enabled. Read/write operations access the buffer

Note: The PWM mode can be used without enabling the buffer register only in one pulse

mode (OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.

Bit 10 OC4FE: Output Compare 4 Fast Enable

This bit speeds the effect of an event on the trigger in input on the OC4 output.

0: OC4 behaves normally depending on the counter and CCR4 values even when the trigger

is ON. The minimum delay to activate OC4 when an edge occurs on the trigger input is 5

clock cycles.

1: An active edge on the trigger input acts like a compare match on the OC4 output. OC4 is

set to the compare level independently from the result of the comparison. Delay to sample

the trigger input and to activate OC4 output is reduced to 3 clock cycles. OC4FE acts only if

the channel is configured in PWM 1 or PWM 2 mode.

Bits [9:8] CC4S[1:0]: Capture / Compare 1 Selection

This configures the channel as an output or an input. If an input, it selects the input source.

00: Channel is an output

01: Channel is an input and is mapped to TI4

10: Channel is an input and is mapped to TI3

11: Channel is an input and is mapped to TRGI. This mode requires an internal trigger input

selected by the TS bit in the TIMx_SMCR register.

Note: CC2S may be written only when the channel is off (CC2E = 0 in the TIMx_CCER

Bit 7 Reserved, must be kept at reset value

Bits [6:4] OC3M[2:0]: Output Compare 1 Mode

See OC4M description above

Bit 3 OC3PE: Output Compare 3 Preload Enable

See OC4PE description above

Bit 2 OC3FE: Output Compare 3 Fast Enable

See OC4FE description above

Bits [1:0] CC3S[1:0]: Capture / Compare 3 Selection

This configures the channel as an output or an input. If an input, it selects the input source.

00: Channel is an output

01: Channel is an input and is mapped to TI3

10: Channel is an input and is mapped to TI4

11: Channel is an input and is mapped to TRGI. This requires an internal trigger input

selected by the TS bit in the TIMx_SMCR register.

Note: CC3S may be written only when the channel is off (CC3E = 0 in the TIMx_CCER

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