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STM32W108HB Datasheet(PDF) 207 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 207 Page - STMicroelectronics |
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207 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 207/278 Input capture mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IC4F[3:0] IC4PSC[1:0] CC4S[1:0] IC3F[3:0] IC3PSC[1:0] CC3S[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Reserved, must be kept at reset value Bits [15:12] IC4F[3:0]: Input Capture 1 Filter This defines the frequency used to sample the TI4 input, fSampling, and the length of the digital filter applied to TI4. The digital filter requires N consecutive samples in the same state before being output. 0000: fSampling = PCLK, no filtering 0001: fSampling = PCLK, N=2 0010: fSampling = PCLK, N=4 0011: fSampling = PCLK, N=8 0100: fSampling = PCLK/2, N=6 0101: fSampling = PCLK/2, N=8 0110: fSampling = PCLK/4, N=6 0111: fSampling = PCLK/4, N=8 1000: fSampling = PCLK/8, N=6 1001: fSampling = PCLK/8, N=8 1010: fSampling = PCLK/16, N=5 1011: fSampling = PCLK/16, N=6 1100: fSampling = PCLK/16, N=8. 1101: fSampling = PCLK/32, N=5 1110: fSampling = PCLK/32, N=6 1111: fSampling = PCLK/32, N=8 Note: PCLK is 12 MHz when using the 24 MHz HSE OSC, and 6 MHz using the 12 MHz HSI RC oscillator. Bits [11:10] IC4PSC[1:0]: Input Capture 1 Prescaler 00: No prescaling, capture each time an edge is detected on the capture input 01: Capture once every 2 events 10: Capture once every 4 events 11: Capture once every 6 events Bits [9:8] CC4S[1:0]: Capture / Compare 1 Selection This configures the channel as an output or an input. If an input, it selects the input source. 00: Channel is an output 01: Channel is an input and is mapped to TI4 10: Channel is an input and is mapped to TI3 11: Channel is an input and is mapped to TRGI. This mode requires an internal trigger input selected by the TS bit in the TIMx_SMCR register. Note: CC2S may be written only when the channel is off (CC2E = 0 in the TIMx_CCER register). |
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