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STM32W108HB Datasheet(PDF) 211 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 211 Page - STMicroelectronics |
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211 / 278 page  STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 211/278 10.3.13 Timer x auto-reload register (TIMx_ARR) Address offset: 0xE02C (TIM1) and 0xF02C (TIM2) Reset value: 0x0000 0000 Reserved, must be kept at reset value ARR[15:0]: Auto-reload value 10.3.14 Timer x capture/compare 1 register (TIMx_CCR1) Address offset: 0xE034 (TIM1) and 0xF034 (TIM2) Reset value: 0x0000 0000 Reserved, must be kept at reset value CCR[15:0]: Capture/compare value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Bits [15:0] ARR[15:0] is the value to be loaded in the shadow auto-reload register. The auto-reload register is buffered. Writing or reading the auto-reload register accesses the buffer register. The content of the buffer register is transfered in the shadow register permanently or at each update event UEV, depending on the auto-reload buffer enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow point (or underflow point when down-counting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The counter is blocked while the auto-reload value is 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits [31:16] Bits [15:0] If the CC1 channel is configured as an output (CC1S = 0): CCR1 is the buffer value to be loaded in the actual capture/compare 1 register. It is loaded permanently if the preload feature is not selected in the TIM1_CCMR1 register (bit OC1PE). Otherwise the buffer value is copied to the shadow capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIM1_CNT and signaled on the OC1 output. If the CC1 channel is configured as an input (CC1S is not 0): CCR1 is the counter value transferred by the last input capture 1 event (IC1). |
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