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MCP1792 Datasheet(PDF) 12 Page - Microchip Technology |
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MCP1792 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 32 page ![]() 2019-2020 Microchip Technology Inc. DS20006229C-page 12 MCP1792/3 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. 3.1 Ground Pin (GND) For optimal noise and Power Supply Rejection Ratio (PSRR) performance, the GND pin of the LDO should be tied to an electrically “quiet” circuit ground. This will ensure the LDO power supply rejection ratio and noise device performance. The GND pin of the LDO conducts only ground current and that is why a wide trace is not required. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower the inductance and, as a result, reduce the effect of fast current tran- sients. 3.2 Regulated Output Voltage Pin (VOUT) The VOUT pin is the regulated output voltage VR of the LDO. A minimum output capacitance of 2.2 µF is required for the LDO to ensure the stability in all the typ- ical applications. The MCP1792/3 is stable with ceramic capacitors. See Section 4.2 “Output Capaci- tance Requirements” for output capacitor selection guidance. 3.3 Input Voltage Supply Pin (VIN) Connect the input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 2.2 µF to 10 µF should be sufficient for most applications. The type of capacitor used is ceramic. However, the low ESR characteristics of the ceramic capacitor will yield better noise and PSRR performance at high frequency. 3.4 Shutdown Control Input (SHDN) The SHDN input is used to turn the LDO output voltage off. When the SHDN input is at a logic high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the LDO enters a low-quiescent current shutdown state, where the typical quiescent current is 2 µA. TABLE 3-1: PIN FUNCTION TABLE SOT 23A-3 SOT 23-5 SOT 223-3 SOT 223-5 Symbol Description 1 2 2 3 GND Ground 25 3 4 VOUT Regulated Output Voltage VR 31 1 2 VIN Input Voltage Supply — 4 — 5 NC Not connected pins (should either be left floating or connected to ground) —3 — 1 SHDN Shutdown Control Input. Connect to GND to turn off the output. Do not leave this pin floating. —— 4 6 Tab Exposed Thermal Pad, connected to GND |
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