MCP1792 datasheet(14/32 Pages) MICROCHIP

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DS20006229C-page 14

MCP1792/3

4.4

Circuit Protection

The MCP1792/3 features current foldback protection

during an output short-circuit event that occurs in nor-

mal operation. When the current foldback block detects

an increase in load current, over the typical value of

230 mA, the output current and output voltage will start

to decrease until the output current reaches a value of

typically 10 mA (see Figure 2-16 and Figure 2-17).

If a short circuit is present during power-up, the part will

enter current limit protection.

The MCP1792/3 was tested using the AEC-Q100 test

set-up in Figure 4-2. The testing conditions require the

use of very high parasitic inductances on the input and

output. For cases like this, it is required to prevent the

output voltage going below ground with more than 1V.

Note that the VOUT pin can withstand a maximum of

-0.3 VDC (see Absolute Maximum Ratings †). This can

be achieved by placing a Schottky diode with the cath-

ode to VOUT and the anode to ground.

Thermal shutdown functionality is present on the

device and adds to the protection features of the part.

Thermal shutdown is triggered at a typical value of

175°C and has a typical hysteresis of 15°C.

FIGURE 4-2:

Short Circuit Test Set-Up.

4.5

Dropout Operation

For VR = 5V, MCP1792/3 can be found operating in a

dropout condition (the minimum input voltage is 4.5V),

which can happen during cold crank event, when the

supply voltage can drop down to 3V. It is preferred to

ensure that the part does not operate in dropout during

DC operation so that the AC performance is main-

tained.

The device has a dropout voltage of approximately

250 mV at full load and room temperature, but because

of the extended temperature range at 150°C, due to

increased leakage at hot, it reaches up to 1200 mV. For

a 5V output, the minimum supply voltage required in

order to have a regulated output, within specification, is

6.2V.

FIGURE 4-3:

Line Step from Dropout.

4.6

Shutdown Input (SHDN) and Input

UVLO

The SHDN input is an active-low input signal that turns

the LDO on and off. The SHDN threshold has a

logic HIGH level of minimum 2.4V and a logic LOW

level of maximum 0.8V.

The SHDN pin ignores low-going pulses that are up to

30 µs. This blanking window helps to reject any system

noise spikes on the SHDN input signal. Then, on the

rising edge of the SHDN input, the shutdown circuitry

adds 770 µs delay before allowing the regulator output

to turn on. This delay helps to reject any false turn-on

signals or noise on the SHDN input signal. After the

(30 + 770) µs delay, the regulator starts charging the

load capacitor as the output rises from 0V to its

regulated value. The charging current amplitude will be

limited by the short circuit current value of the device. If

the SHDN input signal is pulled low during the 800 µs

delay period, the timer will be reset and the delay time

will start over again on the next rising edge of the

SHDN input. Figure 4-4 shows a timing diagram of the

SHDN input.



The MCP1792/3 has an internal discharge transistor

connected to the VOUT PIN that is enabled when the

SHDN pin goes low. The discharge occurs through a

typical resistance of 80

.

VIN

200 ms/div

2V/div

VOUT

2V/div

IOUT = 10 mA

11V

VR = 5V

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