DS0128 datasheet(35/140 Pages) MICROSEMI

35 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

2.3.5.6

Single-Ended I/O Standards

2.3.5.6.1

Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined

by JEDEC (JESD 8-5). The LVCMOS standards supported in IGLOO2 FPGAs and SmartFusion2 SoC

FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33.

2.3.5.6.2

3.3 V LVCMOS/LVTTL

LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V

applications.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 29 •

LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions

(Applicable to MSIO I/O Bank Only)

Parameter

Symbol

Min

Typ Max

Unit

Supply voltage

VDDI

3.15

3.3

3.45

Table 30 •

LVTTL/LVCMOS 3.3 V Input Voltage Specification (Applicable to MSIO I/O

Bank Only)

Parameter

Symbol

Min

Max

Unit

DC input logic high

VIH (DC)

2.0

3.45

DC input logic low

VIL (DC)

–0.3

0.8

Input current high1

See

Table 24, page 23.

IIH (DC)

Input current low1

IIL (DC)

Table 31 •

LVCMOS 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank

Only)

Parameter

Symbol

Min

Max

Unit

DC output logic high1

The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B

requirements.

VOH

VDDI – 0.4

DC output logic low1

VOL

0.4

Table 32 •

LVTTL 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only)

Parameter

Symbol

Min

Max

Unit

DC output logic high

VOH

2.4

DC output logic low

VOL

0.4

Table 33 •

LVTTL/LVCMOS 3.3 V AC Maximum Switching Speed (Applicable to MSIO I/O Bank

Only)

Parameter

Symbol

Max Unit

Conditions

Maximum data rate

(for MSIO I/O bank)

DMAX

600

Mbps AC loading: 17 pF load, maximum

drive/slew

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