DS0128 datasheet(39/140 Pages) MICROSEMI

39 / 140 page

IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

4 mA

Slow

3.095

3.641

2.705

3.182

3.088

3.633

4.738 5.575

4.348

5.116

Medium

2.825

3.324

2.488

2.927

2.823

3.321

4.492 5.285

4.063

4.781

Medium fast 2.701

3.178

2.384

2.804

2.698

3.173

4.364 5.135

3.945

4.642

Fast

2.69

3.165

2.377

2.796

2.687

3.161

4.359 5.129

3.94

4.636

6 mA

Slow

2.919

3.434

2.491

2.93

2.902

3.414

5.085 5.983

4.674

5.5

Medium

2.65

3.118

2.279

2.681

2.642

3.108

4.845 5.701

4.375

5.148

Medium fast 2.529

2.975

2.176

2.56

2.521

2.965

4.724 5.558

4.259

5.011

Fast

2.516

2.96

2.168

2.551

2.508

2.95

4.717 5.55

4.251

5.002

8 mA

Slow

2.863

3.368

2.427

2.855

2.844

3.346

5.196 6.114

4.769

5.612

Medium

2.599

3.058

2.217

2.608

2.59

3.047

4.952 5.827

4.471

5.261

Medium fast 2.483

2.921

2.114

2.487

2.473

2.91

4.832 5.685

4.364

5.134

Fast

2.467

2.902

2.106

2.478

2.457

2.89

4.826 5.678

4.348

5.116

12 mA

Slow

2.747

3.232

2.296

2.701

2.724

3.204

5.39

6.342

4.938

5.81

Medium

2.493

2.934

2.102

2.473

2.483

2.921

5.166 6.078

4.65

5.471

Medium fast 2.382

2.803

2.006

2.36

2.371

2.789

5.067 5.962

4.546

5.349

Fast

2.369

2.787

1.999

2.352

2.357

2.773

5.063 5.958

4.538

5.339

16 mA

Slow

2.677

3.149

2.213

2.604

2.649

3.116

5.575 6.56

5.08

5.977

Medium

2.432

2.862

2.028

2.386

2.421

2.848

5.372 6.32

4.801

5.649

Medium fast 2.324

2.734

1.937

2.278

2.311

2.718

5.297 6.233

4.7

5.531

Fast

2.313

2.721

1.929

2.269

2.3

2.706

5.296 6.231

4.699

5.529

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)

management.

Table 47 •

LVCMOS 2.5 V Transmitter Characteristics for MSIO Bank (Output and Tristate Buffers)

Output

Drive

Selection

Slew

Control

TDP

TZL

TZH

THZ1

TLZ1

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

2 mA

Slow

3.48

4.095

3.855

4.534

3.785

4.453

2.12

2.494

3.45

4.059

4 mA

Slow

2.583

3.039

3.042

3.579

3.138

3.691

4.143 4.874

4.687

5.513

6 mA

Slow

2.392

2.815

2.669

3.139

2.82

3.317

4.909 5.775

5.083

5.98

8 mA

Slow

2.309

2.717

2.565

3.017

2.74

3.223

5.812 6.837

5.523

6.497

12 mA

Slow

2.333

2.745

2.437

2.867

2.626

3.089

6.131 7.213

5.712

6.72

16 mA

Slow

2.412

2.838

2.335

2.747

2.533

2.979

6.54

7.694

6.007

7.067

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)

management.

Table 46 •

LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers)

Output

Drive

Selection

Slew

Control

TDP

TZL

TZH

THZ1

TLZ1

Unit

–1

–Std

–1

–Std

–1

–Std

–1

–Std

–1

–Std

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