DS0128 datasheet(13/140 Pages) MICROSEMI

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Revision History

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0

1.9

Revision 4.0

The following is a summary of the changes in revision 4.0 of this document.

•

Updated Table 1, page 5. Changed the Status of 090 devices to "Production" (SAR 62750).

•

Updated Figure 10, page 70. Removed inverter bubble from DDR_IN latch (SAR 61418).

•

Updated SerDes Electrical and Timing AC and DC Characteristics, page 120 (SAR 62836).

1.10

Revision 3.0

In revision 3.0 of this document, the Theta B/C columns and FCS325 package was updated. For more

information, see Table 9, page 11 (SAR 62002).

1.11

Revision 2.0

The following is a summary of the changes in revision 2.0 of this document.

•

Table 1, page 5 was updated (SAR 59056).

•

Table 7, page 9 temperature and data retention information was updated SAR (61363).

•

Storage Operating Table was updated and split into three tables – Table 5, page 8, Table 7, page 9

(SAR 58725).

•

Updated Theta B/C columns and FCS325 package in Table 9, page 11 (SAR 62002).

•

Added 090-FCS325 thermal resistance to Table 9, page 11 (SAR 59384).

•

TQ144 package was added to Table 9, page 11 (SAR 57708).

•

Added PLL jitter data for the VF400 package (SAR 53162).

•

Added Additional Worst Case IDD to Table 11, page 13 and Table 12, page 14 (SAR 59077).

•

Table 13, page 14, Table 14, page 14, and Table 15, page 15 were added to verify Inrush currents

(SAR 56348).

•

Table 18, page 20 and Table 21, page 21 – I/O speeds were replaced.

•

Max speed was changed in Table 41, page 27 (SAR 57221) and in Table 52, page 30 (SAR 57113).

•

Minimum and Maximum DC/AC Input and Output Levels Specification, page 30 and

Table 49, page 30–Table 57, page 32 were added.

•

Added Cload to Table 89, page 40 (SAR 56238).

•

Removed "Rs" information in DDR Timing Measurement Table 123, page 47, Table 133, page 50,

and Table 144, page 52.

•

Updated drive programming for M/B-LVDS outputs (SAR 58154).

•

Added an inverter bubble to DDR_IN latch in Figure 10, page 70 (SAR 61418).

•

QF waveform in Figure 11, page 71 was updated (SAR 59816).

•

uSRAM Write Clock minimum values were updated in Table 237, page 86–Table 243, page 93 (SAR

55236).

•

Fixed typo in the 32 kHz Crystal (XTAL) oscillator accuracy data section (SAR 59669).

•The "On-Chip Oscillator" section was split, and the Embedded NVM (eNVM) Characteristics,

page 104 was added. Table 277, page 107–Table 281, page 109 were revised.(SARs 57898 and

59669).

•

PLL VCP Frequency and conditions were added to Table 282, page 110 (SAR 57416).

•

Fixed typo for PLL jitter data in the 100-400 MHz range (SAR 60727).

•

Updated FCCC information in Table 282, page 110 and Table 283, page 111 (SAR 60799).

•

Device 025 specifications were added to Table 283, page 111 (SAR 51625).

•JTAG Table 284, page 111 was replaced (SAR 51188).

•

Flash*Freeze Table 293, page 119 was replaced (SAR 57828).

•

Added support for HCSL I/O Standard for SERDES reference clocks in Table 300, page 122 and

Table 301, page 122 (SAR 50748).

•

Tir and Tif parameters were added to Table 303, page 123 (SAR 52203).

•

Speed grade consistency was fixed in tables throughout the datasheet (SAR 50722).

•

Added jitter attenuation information (SAR 59405).

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