FS32R274VCK2VMM datasheet(43/78 Pages) NXP

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Table 34. RMII signal switching specifications

(continued)

Num

Description

Min.

Max.

Unit

RMII8

RMII_CLK to TXD[1:0], TXEN valid

—

RMII7

RMII8

Valid data

RMII2

RMII1

RMII_CLK (input)

TXD[n:0]

TXER

Figure 12. RMII transmit signal timing diagram

RMII2

RMII1

RMII4

RMII3

Valid data

RMII_CLK (input)

RXD[n:0]

CRS_DV

RXER

Figure 13. RMII receive signal timing diagram

9.1.3 RGMII signal switching specifications

The RGMII interface works at 3.3 V compatible levels as mentioned in RGMII pad DC

electrical characteristics.

The following timing specs meet the requirements for RGMII style interfaces for a range

of transceiver devices.

• Measurements are with input transition of 0.750 ns and output load of 10 pF.

Table 35. RGMII signal switching specifications

Symbol

Description

Min

Typ

Max

Unit

Notes

—

Input Duty cycle (Clock from external PHY)

—

Tcyc

Clock cycle duration

7.2

8.0

8.8

TskewT

Data to clock output skew at transmitter

-500

500

TskewR

Data to clock input skew at receiver

1.8

2.6

Table continues on the next page...

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S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

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