FS32R274VCK2VMM datasheet(73/78 Pages) NXP

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17.1 Reset sequence duration

Table 57 specifies the minimum and the maximum reset sequence duration for the five

different reset sequences described in Reset sequence description.

Table 57. RESET sequences

No.

Symbol

Parameter

TReset

Unit

Min

Typ

Max1

TDRB

Destructive Reset Sequence, BIST enabled

502

TDR

Destructive Reset Sequence, BIST disabled

400

2000

µs

TERLB

External Reset Sequence Long, BIST enabled

TFRL

Functional Reset Sequence Long, BIST disabled

400

2000

µs

TFRS

Functional Reset Sequence Short3

500

µs

1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET

by an external reset generator.

2. Max time is based on STCU BIST configuration execution time + max RESET time (TDR). For default STCU BIST

configuration execution time, refer to EB834. Contact your NXP sales representative for details.

3. BIST is not executed on short functional reset

17.2 Reset sequence description

The figures in this section show the internal states of the device during the five different

reset sequences. The doted lines in the figures indicate the starting point and the end point

for which the duration is specified in Table 57.

With the beginning of DRUN mode, the first instruction is fetched and executed. At this

point, application execution starts and the internal reset sequence is finished.

The SMPS self test is always triggered during Phase3 after a destructive reset so that

duration is included into Phase3 below.

In external regulation mode, the VREG_POR_B pin should be de-asserted only when all

the design supplies are in operating range. Deassertion of VREG_POR_B pin triggers the

start of reset sequence in internal as well as external regulation modes.

The following figures show the internal states of the device during the execution of the

reset sequence and the possible states of the RESET_B signal pin.

NOTE

RESET_B is a bidirectional pin. The voltage level on this pin

can either be driven low by an external reset generator or by the

device internal reset circuitry. A high level on this pin can only

Reset sequence

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VCK2VMM Datasheet(PDF) 73 Page - NXP Semiconductors

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