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DSP96002UM/AD Datasheet(PDF) 55 Page - NXP Semiconductors |
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DSP96002UM/AD Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 111 page  Specifications AC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-33 189 CLK Low to DSO (ACK) Valid (Enter Debug Mode) • After Synchronous Recovery from STOP State • After Synchronous Recovery from WAIT State 54019 51020 — — 45019 42520 — — 30519 29020 — — ns ns 190 DR Asserted to DSO (ACK) Valid (Enter Debug Mode) • After Asynchronous Recovery from STOP State • After Asynchronous Recovery from WAIT State 54019 51020 — — 45019 42520 — — 30519 29020 — — ns ns 191 DMA Request Asserted to CLK Low (Setup)6 6—5—5— ns 192 CLK Low to DMA Request Invalid (Hold)6 2—2— 1.5 — ns 193 CLK Low to External DMA Access Valid 7621 — 63.521 —5021 —ns 194 DR Assertion Width • To recover from WAIT/STOP • To recover from WAIT/STOP and enter Debug Mode 3522 42025 30023 — 2924 35025 25023 — 2324 23525 20023 — ns ns Note: 1. The numbers in this column are shown as circled numbers in the following figures. 2. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V ± 10%, GND = 0 V DC, TJ = –40°C to 100°C at 40 or 60 MHz: VCC = 5.0 V ± 5%, GND = 0 V DC, TJ = –40°C to 100°C 3. Assuming duty cycle in the range 46.7%–53.3% and no wait states. 4. Assuming duty cycle in the range 46%–54%% and no wait states. 5. Assuming bus ownership. 6. IRQ pin internally defined as DMA request. Table 2-12 WAIT, STOP, DMA Request Timing (Continued) No.1 Characteristic2 33.3 MHz3 40 MHz4 60 MHz4 Unit Min Max Min Max Min Max 7. 13Tc + Tl + 2 8. 13Tc + Tl + 14 9. 13Tc + Tl + 12 10. Tc + 5 11. 14Tc + Tl + 30 12. 14Tc + Tl + 25 13. Tc 14. 12Tc + Tl + 2 15. 12Tc + Tl + 14 16. 12Tc + Tl + 12 17. 13Tc + Tl + 30 18. 13Tc + Tl + 25 19. 18Tc 20. 17Tc 21. 2Tc + Tl + 2 22. Tc + 5 23. 10Tc 24. Tc + 4 25. 14Tc Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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