DSP96002UMSLASHAD datasheet(12/111 Pages) NXP

12 / 111 page

Signal/Connection Descriptions

Port A and Port B

1-8

DSP96002/D, Rev. 2

MOTOROLA

ATT

BTT

Output

Tri-stated

Transfer Type

—TT is an output when the DSP is the bus

master and tri-stated when it is not a bus master. When the

DSP is the bus master, TT is controlled by an on-chip page

circuit. TT is asserted when a fast access memory mode

(Page, Static Column, Nibble or Serial Shift Register) is

detected. If the external bus is not used during an

instruction cycle, or a fault is detected by the page circuit

during an external access, TT remains deasserted. The

parameters of the page circuit fault detection are user

programmable.

ATS

BTS

Input

Output

Tri-stated

Transfer Strobe—

TS is an output when the DSP is the bus

master and an input when it is not a bus master. When the

DSP is the bus master, TS is asserted to indicate that the

address lines A0–A31, S1, S0, BS, BL and R/W are stable

and that a bus read or bus write transfer is taking place.

During a read cycle, input data is latched inside the

DSP96002 on the rising edge of TS. During a write cycle,

output data is placed on the data bus after TS is asserted.

Therefore, TS can be used as an output enable control for

external data bus buffers if they are present. If the external

bus is not used during an instruction cycle, TS remains

deasserted until the next external bus cycle. An external

flip-flop can delay TS, if required, for slow devices or more

address decoding time. The TS pin is also the Host Interface

transfer strobe input used to enable the data bus output

drivers during host read operations and to latch data inside

the Host Interface during host write operations. As an

input, TS may change asynchronously relative to the input

clock. Write data is latched inside the Host Interface on the

rising edge of TS. When the DSP is the bus master, the

combination of BS and TS can be decoded externally to

determine the status of the current bus cycle and to

generate hardware strobes useful for latching address and

data signals.

Table 1-6

Port A and Port B (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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