DSP96002UMSLASHAD datasheet(10/111 Pages) NXP

10 / 111 page

Signal/Connection Descriptions

Port A and Port B

1-6

DSP96002/D, Rev. 2

MOTOROLA

PORT A AND PORT B

Port A and Port B are identical in pinout and function. The following pin

descriptions apply to both ports. Each port may be a bus master and each port has

a slave Host Interface which can be accessed on demand.

MODC/IRQC

Input Input

Mode Select C/External Interrupt Request C—

This input

is internally synchronized to the input clock (CLK).

MODC/IRQC selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA,

MODB and MODC select one of eight initial chip

operating modes latched into the Operating Mode

IRQC is asserted synchronous to the input clock (CLK),

multiple processors can be resynchronized by using the

WAIT instruction and asserting IRQC to exit the Wait

state.

Table 1-6

Port A and Port B

Signal

Name

Type

State

During

Reset

Signal Description

AA0–AA31

BA0–BA31

Input

Output

Tri-stated

Address Bus—

A0–A31 specify the address for external

program and data memory accesses. If there is no external

bus activity, A0–A31 remain at their previous values. The

Address Enable (AE) input acts as an output enable control

for A0–A31. A0–A31 are stable whenever the transfer

strobe TS is asserted and may change only when TS is

deasserted. The signal direction depends on whether the

DSP is the bus master:

•

Bus Master

—A0–A31 are tri-state, active high

outputs.

•

Not a Bus Master

—A2–A5 are active high inputs

used to select the Host Interface register. Lines A0–

A1 and A6–A31 are tri-stated. As inputs, A2–A5

may change asynchronously relative to the input

clock (CLK).

Table 1-5

Interrupt and Mode Control (Continued)

Signal Name

Type

State During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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