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ADV7393 Datasheet(PDF) 12 Page - Analog Devices |
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ADV7393 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 12 of 96 Y0 Y1 Y2 Y3 a Cr2 Cb2 Cr0 Cb0 b Y OUTPUT HSYNC VSYNC a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. PIXEL PORT PIXEL PORT* Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Cb0 Y0 Cr0 Y1 a a(MIN) = 244 CLOCK CYCLES FOR 525p. a(MIN) = 264 CLOCK CYCLES FOR 625p. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. HSYNC VSYNC b Y OUTPUT PIXEL PORT Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram |
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