AD9923ABBCZ datasheet(56/88 Pages) AD

56 / 88 page

AD9923A

Rev. 0 | Page 56 of 88

6dB ~ 42dB

CCDIN

CLI

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

12-BIT

ADC

VGA

DAC

CDS

INTERNAL

VREF

2V FULL SCALE

PRECISION

TIMING

GENERATION

SHP

SHD

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT PHASE

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

CLPOB PBLK

PBLK

1.0V

2.0V

DOUT

DCLK

AD9923A

0.1µF

VGA GAIN

0.1µF 0.1µF

CLAMP LEVEL

DOUT

DLY

DCLK

MODE

FIXED

DELAY

CLI

Figure 73. Analog Front End Functional Block Diagram

ANALOG FRONT END DESCRIPTION/OPERATION

The AD9923A signal processing chain is shown in Figure 73.

Each step is essential to achieve a high quality image from the

raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc restore

circuit is used with an external 0.1 μF series coupling capacitor.

This restores the dc level of the CCD signal to approximately 1.5 V

so that it is compatible with the 3 V supply voltage of the AD9923A.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract video

information and reject low frequency noise. The timing shown in

Figure 20 illustrates how the two internally generated CDS

clocks, SHP and SHD, are used to sample the reference and data

levels of the CCD signal, respectively. The placement of the SHP

and SHD sampling edges is determined by the setting of the

SHPLOC and SHDLOC registers located at Address 0x37.

Placement of these clock signals is critical to achieve the best

CCD performance.

The CDS gain can be set to −3 dB, 0 dB (default), +3 dB, or +6 dB

in the CDSGAIN register, Address 0x04. The +3 dB and +6 dB

settings improve noise performance, but reduce the input range

(see Figure 8).

Variable Gain Amplifier

The VGA stage provides gain in the range of 6 dB to 42 dB,

programmable with 10-bit resolution through the serial digital

interface. A minimum gain of 6 dB is needed to match a 1 V input

signal with an ADC full-scale range of 2 V. When compared to 1 V

full-scale systems, the equivalent range of gain is 0 dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value

using the following equation

Gain (dB) = (0.0358 × Code) + 5.5 dB

where the code range is 0 to 1023.

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 74. VGA Gain Curve

ADC

The AD9923A uses a high performance ADC architecture

optimized for high speed and low power. Differential nonlin-

earity (DNL) performance is typically better than 1 LSB. The

ADC uses a 2 V input range. See Figure 6 and Figure 8 for

typical linearity and noise performance plots.

AD9923ABBCZ Datasheet(PDF) 56 Page - Analog Devices

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