AD9923ABBCZ datasheet(58/88 Pages) AD

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AD9923A

Rev. 0 | Page 58 of 88

Recommended Power-Up Sequence for Master Mode

When the AD9923A is powered up, the following sequence is

recommended (see Figure 75):

Turn on the +3 V power supplies for the AD9923A, and

start the master clock (CLI).

Turn on the V-driver supplies (VH and VL). There are no

restrictions on the order in which VH and VL are turned on.

Reset the internal AD9923A registers by writing 1 to the

SW_RST register (Address 0x10).

Load the required registers to configure the required

VPAT group, V-sequence, field timing information, high

speed timing, horizontal timing, and shutter timing

information.

To place the part into normal power operation, write 0x04

to the AFE STANDBY register (Bits[1:0], Address 0x00)

and 0x60 to TEST3 Register 0xEA. If the CLO output is

being used to drive a crystal, also power up the CLO

oscillator by writing 1 to Register 0x16.

By default, the internal timing core is held in a reset state

with TGCORE_RSTB register = 0. Write 1 to the

TGCORE_RSTB register (Address 0x15) to start the

internal timing core operation. If a 2× clock is used for the

CLI input, set the CLIDIVIDE register (Address 0x30) to

1 before resetting the timing core. It is important to wait

at least 500 μs after starting the master clock (CLI) before

resetting the timing core, especially if using a crystal or

crystal oscillator.

Configure the AD9923A for master mode timing by

writing 1 to the MASTER register (Address 0x20).

Bring the VDR_EN signal high to +3 V to enable the

V-driver outputs. If VDR_EN = 0 V, all V-driver outputs =

VM, and SUBCK = VLL.

Write 1 to the OUTCONTROL register (Address 0x11).

This allows the outputs to become active after the next

SYNC rising edge.

10.

Generate a SYNC event. If SYNC is high at power-up,

bring SYNC input low for a minimum of 100 ns. Then,

bring SYNC high. This causes the internal counters to

reset and starts a VD/HD operation. The first VD/HD

edge allows VD register updates to occur, including

OUTCONTROL to enable all outputs. If an external

SYNC pulse is not available, generate an internal SYNC

pulse by writing to the SYNCPOL register as described in

the Generating Software Sync Without External Sync

Signal section.

POWER

SUPPLIES

SERIAL

WRITES

(OUTPUT)

FIRST FIELD

SYNC

(INPUT)

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUTCONTROL

H1/H3, RG, DCLK, STROBE, MSHUT, VSUB

CLI

(INPUT)

(OUTPUT)

tSYNC

VH SUPPLY

VL SUPPLY

(HI-Z BY DEFAULT)

779

+3V SUPPLIES

VDR_EN

(AND INTERNAL XV1 TO XV13, VSG1 TO VSG8, XSBUCK, XSUBCNT)

+3V

V1 TO V13

Figure 75. Recommended Power-Up Sequence and Synchronization, Master Mode

AD9923ABBCZ Datasheet(PDF) 58 Page - Analog Devices

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