AD9923ABBCZ datasheet(60/88 Pages) AD

60 / 88 page

AD9923A

Rev. 0 | Page 60 of 88

H-COUNTER

RESET

NOTES

1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.

2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.

3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 33 OR 34 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.

4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 34 CLI RISING EDGES AFTER HD FALLING EDGE.

CLI

XX XX

H-COUNTER

(PIXEL COUNTER)

3ns MIN

XXX

3ns MIN

SHD

INTERNAL

tCLIDLY

32.5 CYCLES

012

XXX

Figure 77. External VD/HD and Internal H-Counter Synchronization, Slave Mode

123

H-COUNTER

RESET

NOTES

1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.

H-COUNTER

(PIXEL COUNTER)

N-1

N-2

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

N-3

N-4

N-5

N-6

N-7

N-8

N-9

N-10

N-11

N-12

N-13

N-14

N-15

N-16

N-17

N-18

N-19

N-20

N-21

N-22

N-23

N-24

N-25

N-26

N-27

N-28

Figure 78. Toggle Position Inhibited Area—Master Mode

H-COUNTER

RESET

NOTES

1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.

H-COUNTER

(PIXEL COUNTER)

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

N-1

N-2

N-3

N-4

N-5

N-6

N-7

N-8

N-9

N-10

N-11

N-12

N-13

N-14

N-15

N-16

N-17

N-18

N-19

N-20

N-21

N-22

N-23

N-24

N-25

N-26

N-27

N-28

N-29

N-30

N-31

N-32

N-33

Figure 79. Toggle Position Inhibited Area—Slave Mode

Vertical Toggle Position Placement Near Counter Reset

One additional consideration during the reset of the internal

counters is the vertical toggle position placement. Prior to the

internal counters being reset, there is a region of 28 pixels

during which no toggle positions can be programmed.

As shown in Figure 78, in master mode, the last 28 pixels before

the HD falling edge should not be used for toggle position place-

ment of the XV, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.

Figure 79 shows the same example for slave mode. The same

restriction applies—the last 28 pixels before the counters are

reset cannot be used. However, the counter reset is delayed with

respect to VD/HD placement; therefore, the inhibited area is

different than it is in master mode.

It is also recommended that Pixel Location 0 is not used for

toggle positions for the VSG and SUBCK pulses.

AD9923ABBCZ Datasheet(PDF) 60 Page - Analog Devices

AD9923ABBCZ Datasheet(HTML) 60 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL