TMPR4925 datasheet(109/590 Pages) TOSHIBA

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Chapter 6 Clocks

6-5

6.2

Power-Down Mode

6.2.1

Halt Mode and Doze Mode

The WAIT instruction causes the TX49/H2 core to enter either of the two low-power modes: Halt and

Doze. The TX49/H2 can exit from Halt or Doze mode upon an interrupt exception. Ensure, therefore,

that the TX49/H2 does not enter Halt or Doze mode when all interrupts are masked in the interrupt

controller.

The HALT bit of the TX49/H2 core Config register is used to select Halt or Doze mode. As the

TX4925 does not use the snoop function of the TX49/H2 core, the bit should be set to select Halt mode,

which achieves greater power reduction than Doze mode.

Setting PDNCTR.STPCPU to 1 and then executing the WAIT instruction can stop the clock input to

the TX49/H2 core, thus further reducing power dissipation.

The PDNCTR.STPCPU bit is not automatically cleared to 0 when the device exits from Halt or Doze

mode. To subsequently reenter Halt or Doze mode, first clear the bit to 0 in the program.

6.2.2

Power Reduction for Peripheral Modules

When the system does not use the DMA controller, PCI controller, CHI module, serial I/O controller,

timers/counters, SPI module, parallel I/O controller, or AC-link controller, it can stop the input clock for

that module to reduce power dissipation.

The clock control register (CLKCTR) is used to control whether to turn each clock on or off. The

module should be reset before its clock can be turned on or off. This reset is performed using the reset

bit for the specific module, provided in the clock control register. The reset also initializes the registers

of the module, thus requiring subsequent setup of necessary register values and other configurations.

Refer to Section 5.2.9, “Clock Control Register” for detail of the clock control register (CLKCTR).

6.2.3

Power-Down Mode

Setting the PDNCTR.PDN bit to 1 can stop all clocks output from the CG. This also stops the PLL.

In this state, only the RTC operates with the 32 kHz clock.

There is some delay between the time when the PDNCTR.PDN bit is set to 1 and the time when the

PLL and clock outputs actually stop. To prevent a bus cycle from occurring during power-down or

power-up transition, execute the program from cache.

Use an external interrupt or RTC interrupt to exit from power-down mode. PDNCTR.PDNMSK

specifies which interrupt will be used. Note that if the device enters power-down mode with all

interrupts disabled, you can only restore device operation by resetting it.

The PDNCTR.PDN bit is not automatically cleared to 0 when the device exits from power-down

mode. To subsequently reenter power-down mode, first clear the bit to 0 in the program.

TMPR4925 Datasheet(PDF) 109 Page - Toshiba Semiconductor