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TMPR4925 Datasheet(PDF) 105 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 105 Page - Toshiba Semiconductor |
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105 / 590 page  Chapter 6 Clocks 6-1 6. Clocks 6.1 TX4925 Clock Signals Figure 6.1.1 shows the configuration of TX4925 blocks and clock signals. Table 6.1.1 describes each clock signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is 200 MHz. Figure 6.1.1 TX4925 Block and Clock Configuration SDCLK[1:0] C32OUT TCLK PDNCTR.STPCPU CLKCTR TX4925 DMACKE PCICKE PIOCKE TMR2CKE TMR1CKE TMR0CKE SIO1CKE CLKGATE TMR2 TMR1 TMR0 SIO1 SIO0 SIO0CKE SCLK CHICKE ACLC SPI RTC BC32K OSC C32IN ACLCKE SPICKE BITCLK PCIC IRC PIO CHI CHICLK MASTERCLK OSC CCFG.RF CLKGATE IMBUSCLKF 1/2 GBUSCLKF 1/2 DMAC EBUSC NDFMC 1/8 SDRAMC TX49/H2 Core CPUCLK GBUSCLK CG SYSCLK SDCLKIN PCICLK[2:1] DATA latch PLL ADDR[4:3] PCI External Device SDRAM EJTAG/DSU TCK DCLK 1/6 Refresh Counter 1/1 1/2 1/4 1/8 x2.5 x4 1/1 1/2 1/4 1/1 1/2 1/3 1/4 PCICLK_IO |
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