74HC4024

7-stage binary ripple counter

Rev. 10 — 23 November 2018

Product data sheet

1. General description

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The

counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages

and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle

flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess of VCC.

2. Features and benefits

• Low-power dissipation

• Complies with JEDEC standard no. 7A

• CMOS input levels

• ESD protection:

• HBM JESD22-A114F exceeds 2 000 V

• MM JESD22-A115-A exceeds 200 V.

• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.

3. Applications

• Frequency dividing circuits

• Time delay circuits.

4. Ordering information

Table 1. Ordering information

Package

Type number

Temperature range

Name

Description

Version

74HC4024D

-40 °C to +125 °C

SO14

plastic small outline package;

14 leads; body width 3.9 mm

SOT108-1