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UPD17062 Datasheet(PDF) 53 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 53 Page - Renesas Technology Corp |
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53 / 298 page ![]() 51 µPD17062 Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register and Data Memory Row Address Pointer BANK : Bank register IX : Index register IXE : Index enable flag IXH : Bits 10 to 8 of the index register IXM : Bits 7 to 4 of the index register IXL : Bits 3 to 0 of the index register m : Data memory address specified with mR and mC mR : Data memory row address (high order) mC : Data memory column address (low order) MP : Data memory row address pointer MPE : Memory pointer enable flag r : General-purpose register column address RP : General-purpose register pointer ( ×) : Contents addressed by × b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 IXE MPE 00 01 10 11 RP r BANK m BANK mR (r) (r) MP BANK m BANK mR (r) MP (r) IXH, IXM IX Logical OR General-purpose register address specified with r Data memory address specified with m Indirect transfer address specified with @r Bank Row address Column address Bank Row address Column address Bank Row address Column address Same as above Same as above Same as above Same as above Same as above Logical OR |
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