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UPD17062 Datasheet(PDF) 86 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 298 page ![]() 84 µPD17062 9.20 IDCEN (31H) 9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) b3 b2 b1 b0 0 0 IDCEN 31H 0 1 0 IDC operation prohibited (display off) IDC operation start (display on) b3 b2 b1 b0 PLULSEN3 32H 0 0 1 1 0 1 0 1 PLULSEN2 PLULSEN1 PLULSEN0 1.25 to 1.5 s or more 3.5 to 3.75 s or more 0.25 to 0.5 s or more Unlock flip-flop disable (always set) Fixed at 0 Setting of the delay time of the reference frequency fr and divided frequency fN required for setting the unlock flip-flop µ µ µ |
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