UPD17062 datasheet(123/298 Pages) RENESAS

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121

µPD17062

11.7

EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN)

There are two external interrupt sources: INTNC and VSYNC.

An interrupt request is issued when a rising or falling edge is input to the INTNC or VSYNC pin.

11.7.1

Configuration

Fig. 11-5 shows the configurations of the INTNC and VSYNC interrupts.

As shown in Fig. 11-5, the INTNC and VSYNC signals are input to the INTNC or INTVSYN latch and to edge

detectors.

The edge detectors output their respective interrupt request signals according to the inputs from the pin

and the status of the IEGNC or IEGVSYN flip-flop.

The IEGNC flip-flop and IEGVSYN flip-flop correspond to the IEGNC flag and IEGVSYN flag, respectively,

in the interrupt edge selection register (INTEDGE: address 1FH) of the control register.

The INTNC latch and INTVSYN latch correspond to the INTNC flag and INTVSYN flag, respectively, in the

interrupt-pin-level judge register (INTJDG: address 0FH) of the control register.

The Schmitt triggers at the INTNC and VSYNC inputs prevent pulses operations due to noise. These pins do

not accept pulses of 1

µs or less.

A minimum pulse width can be set for the INTNC pin. See Section 9.10.

Fig. 11-5

INT0 Pin and INT1 Pin Configurations

IRQNC

IRQVSYN

INTNC latch

INTVSYN latch

IEGVSYN flip-flop

0 FH

1 FH

b3 b2 b1

b0 b3 b2 b1 b0

Control register

Name

Address

Bit

Flag

symbol

Interrupt

edge select

(INTEDGE)

Interrupt

pin level judge

(INTJDG)

VSYNC pin

INTNC pin

Schmitt trigger

IEGNC flip-flop

Edge detection

Interrupt request block

Edge detection

Schmitt trigger

UPD17062 Datasheet(PDF) 123 Page - Renesas Technology Corp

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