RT3624LE datasheet(43/48 Pages) RICHTEK

43 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

DS3624LE-00

April

2022

www.richtek.com

Sum OCP threshold

Inductor Current

VID

VR_READY

Sum OCP trigger

μs

Mask sum OCP

Inductor current>Sum OCP threshold

μs

Figure 22. SUM OC Protection Mechanism

Over-Voltage Protection (OVP)

The

OVP

threshold

linked

with

VID.

The

classification table is illustrated in Table 17. While VID

= 0V, OVP is masked. When VID ramps up from VID =

0V till the first PWM after VID settles, OVP threshold is

2.45V to allow not-fully-discharged VSEN. Otherwise,

the OVP threshold is relative to VID and equals to

VID+350mV with minimum limit = 1.35V. While VID

≤

1.0V, the OVP threshold is limited at 1.35V.

The OV protection mechanism is illustrated in Figure

23 and Figure 24. When OVP is triggered with 0.5

µs

filter time, controller de-asserts VR_READY and forces

all PWMs low to turn on low-side power MOSFETs.

PWM remains low until the output voltage is pulled

down to below 2.1V for DVID up from 0V and below

VID for other conditions. After 60

µs from OVP trigger,

VID starts to ramp down to 0V with slow slew rate.

During the period, PWM is not allowed to turn on.

Controller controls PWM to be low or tri-state to pull

down the output voltage along with VID.

RT3624LE Datasheet(PDF) 43 Page - Richtek Technology Corporation

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