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RT3624LE Datasheet(PDF) 17 Page - Richtek Technology Corporation |
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RT3624LE Datasheet(HTML) 17 Page - Richtek Technology Corporation |
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17 / 48 page ![]() RT3624LE Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS3624LE-00 April 2022 www.richtek.com 17 Application Information The RT3624LE includes two voltage rails: a 4/3/2/1 phase synchronous buck controller, the GTUS VR, and a 2/1 phase synchronous buck controller, the VCCSA VR, designed to meet Intel IMVP9.1 compatible CPUs specification with a serial SVID control interface. The controller uses an ADC to implement all kinds of settings to save total pin number for easy use increasing PCB space utilization. The RT3624LE is used in desktop computers or notebook computers. Power-ON Sequence In order to confirm sufficient power supply for proper operation, the VR triggers UVLO if VCC voltage drops below 4.2V (max). UVLO protection shuts down controller and forces high-side MOSFET and low-side MOSFET off. When VCC > 4.45V(max), RT3624LE issues POR=high and waits for VRON signal. After POR=high and VRON > 0.7V, controller powers on (Chip Enable = H) and starts VR internal settings, which include internal circuit offset correction and function settings (PIN-SETTING). Users can set multi-functions through SETx, TSEN and TSENA pins. Figure 2 shows the typical timing of controller power-on. The pull-high power of VRON pin is recommended as 1.05V, the same power for SVID interface. That can ensure SVID power is ready while VRON = H. Driver power (PVCC) is strongly suggested to be ready after VCC. This can prevent current flow back to VCC from PVCC through PWMx pin or DRVEN pin. VR Initial Setting Mode Chip Enable (VRON=H and VCC>4.45V) VR_READY VSEN Internal Setting PVCC VCC VRON Figure 2. Typical Timing of Controller Power-ON Maximum Active Phases Number Setting The number of active phases is determined by ISENxN voltages. The detection is only active and latched at Chip Enable rising edge (VRON = H and VCC > 4.45V). While voltage at ISENxN > (VCC − 0.5V), maximum active phase number is (x-1). For example, pulling ISEN4N to VCC programs a 3-phase operation, while pulling ISEN3N to VCC programs a 2-phase operation. The unused ISENxP pins are recommended to connect to VCC and the unused PWM pins can be floating. Figure 3 is a 3-phase operation example. |
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