AT43USB325 datasheet(76/109 Pages) ATMEL

76 / 109 page

3355C–USB–4/05

AT43USB325

8.3.8

Hub Endpoint 0 Service Routine Register – HCSR0

8.3.9

Function Endpoint 0 Service Routine Register – FCSR0

• Bit 7..4 – Reserved

These bits are reserved in the AT43USB325 and will read as zero.

• Bit 3 – STALL SENT

The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this

bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is cleared

indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowledge

• Bit 2 – RX SETUP: Setup Packet Received

This bit is used by control endpoints only to signal to the microcontroller that the USB hardware

has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO.

The hardware will clear all other bits in this register while setting RX SETUP. If interrupt is

enabled, the microcontroller will be interrupted when RX SETUP is set. After the completion of

reading the data from the FIFO, firmware should clear this bit by writing a one to the

RX_SETUP_ACK bit of the Control and Acknowledge Register.

• Bit 1 – RX OUT PACKET

The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO.

While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not overwrite

the data in the FIFO except for an early set-up. RX OUT Packet is used for the following

operations:

Control write transactions by a control endpoint.

OUT transaction with DATA1 PID to complete the status phase of a control endpoint.

Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears

this bit after the FIFO contents have been read by writing a one to the RX_OUT_PACKET_ACK

bit of the Control and Acknowledge Register.

• Bit 0 – TX COMPL: Transmit Completed

This bit is used by a control endpoint hardware to signal to the microcontroller that it has suc-

cessfully completed certain transactions. TX Complete is set at the completion of a:

Control read data stage.

Status stage without data stage.

Status stage after a control write transaction.

This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit of

the Control and Acknowledge Register.

Bit

Function EP0 $1FDF

–

STALL SENT

RX SETUP

RX OUT PACKET

TX COMPLETE

HCSR0

Function EP0 $1FDD

–

STALL SENT

RX SETUP

RX OUT PACKET

TX COMPLETE

FCSR0

Read/Write

Initial Value

AT43USB325 Datasheet(PDF) 76 Page - ATMEL Corporation

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