AT43USB325 datasheet(40/109 Pages) ATMEL

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3355C–USB–4/05

AT43USB325

AVR Register Set

5.1

Status Register and Stack Pointer

5.1.1

Status Register – SREG

•Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual

interrupt enable control is then performed in separate control registers. If the global interrupt

enable bit is cleared (zero), none of the interrupts are enabled independent of the individual

interrupt enable settings. The I-bit is cleared by the hardware after an interrupt has occurred,

and is set by the RETI instruction to enable subsequent interrupts.

•Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and desti-

nation for the operated bit. A bit from a register in the register file can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD

instruction.

•Bit 5 – H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set

Description for detailed information.

•Bit 4 – S: Sign Bit, S = N

⊕V

The S-bit is always an exclusive or between the negative flag N and the two's complement over-

flow flag V. See the Instruction Set Description for detailed information.

•Bit 3 – V: Two's Complement Overflow Flag

The two's complement overflow flag V supports two's complement arithmetics. See the Instruc-

tion Set Description for detailed information.

•Bit 2 – N: Negative Flag

The negative flag N indicates a negative result after the different arithmetic and logic operations.

See the Instruction Set Description for detailed information.

•Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the

Instruction Set Description for detailed information.

•Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set

Description for detailed information.

Note that the status register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt routine. This must be handled by software.

Bit

$3F ($5F)

SREG

Read/Write

R/W

Initial Value

AT43USB325 Datasheet(PDF) 40 Page - ATMEL Corporation

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